Multi-Die Test Data Transfer Beyond JTAG I/O Limits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Structural pattern testing in multi-die systems has become slow and expensive due to the limitations of I/O pins and increased circuitry complexity without proportional increases in pin speed or number, especially when using JTAG standards.
Innovation Solution
Implementing a high-bandwidth data transfer mechanism using D2D links, cross die bridges, and DMA controllers within multi-die systems to facilitate efficient packetized test data transfer via PCIe interfaces, allowing dies to function as primary or secondary units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If JTAG standards are used for structural pattern testing in multi-die systems, then testing can be performed using standard protocols, but testing speed decreases and costs increase due to I/O pin limitations
Solution Approach 1:
The system divides the multi-die package into multiple die groups, each with its own dedicated test data interface. This segmentation allows parallel testing of multiple die groups simultaneously, increasing overall testing throughput and speed while maintaining compatibility with standard testing protocols.
Solution Approach 2:
The patent introduces a new dimension for test data transfer by implementing dedicated test data interfaces separate from the standard I/O pins. This creates an additional data pathway that operates independently from the conventional JTAG pin structure, enabling high-speed parallel data transfer without being constrained by the limited number and speed of traditional I/O pins.
2Quantity of substance
If more I/O pins are added to increase testing bandwidth, then data transfer capacity increases, but device complexity and manufacturing costs increase proportionally
Solution Approach 1:
The dedicated test data interfaces are designed to serve multiple functions: they can transfer test patterns to multiple die groups, retrieve test responses from multiple die groups, and operate in conjunction with existing JTAG protocols. This multi-functionality achieves high bandwidth without requiring separate dedicated pins for each function, thereby reducing overall package complexity.
Solution Approach 2:
Instead of adding numerous individual I/O pins, the system uses a smaller number of dedicated test data interfaces that can be replicated or multiplexed to serve multiple die groups. This copying approach provides the necessary bandwidth through interface multiplication rather than pin multiplication, reducing the physical complexity of the package.
3Speed
If I/O pin speed is increased to improve testing throughput, then data transfer rate increases, but manufacturing precision requirements and costs increase
Solution Approach 1:
The system segments the testing workload across multiple dedicated test data interfaces, each operating at moderate speeds. By dividing the total data transfer requirement across multiple parallel interfaces, the system achieves high aggregate throughput without requiring any single interface to operate at extremely high speeds, thereby avoiding the manufacturing precision challenges associated with high-speed pin design.
Solution Approach 2:
The patent moves the high-speed data transfer function from the traditional I/O pin domain to a dedicated test data interface domain. This dimensional separation allows the dedicated interfaces to be optimized specifically for high-speed test data transfer without the constraints and precision requirements of general-purpose I/O pins, enabling higher effective speeds with relaxed manufacturing tolerances.
4Measurement precision
If ATE platform capabilities are increased to handle complex multi-die testing, then testing accuracy improves, but equipment costs increase significantly
Solution Approach 1:
Each die group is equipped with its own dedicated test data interface and can be tested independently or in parallel. This self-service capability allows the testing system to handle complex multi-die configurations without requiring proportionally complex ATE platforms, as each die group can be tested autonomously through its dedicated interface, reducing the overall equipment cost while maintaining testing accuracy.
Solution Approach 2:
By segmenting the multi-die system into independently testable die groups with dedicated interfaces, the patent reduces the complexity burden on the ATE platform. The ATE only needs to manage multiple independent test channels rather than handling complex inter-die interactions, thereby achieving high test accuracy for complex systems without requiring proportionally expensive equipment.
Data Source
AI summary
An integrated circuit package includes two or more discrete semiconductor dies coupled to a package substrate. The dies include a primary die and at least one secondary die. The primary die includes an external data transfer interface, a direct memory access (“DMA”) controller, a primary cross-die bridge, and at least one primary die-to-die interface. At least one of the secondary dies includes a secondary test controller, a secondary cross-die bridge, and a secondary die-to-die interface. A secondary die is operable to send a test data read request to a host system and to receive a test data read response therefrom. The secondary die is further operable to cause a test to be performed on circuitry within the die responsive to contents in the test data read response.