Multi-Die Testing via Secondary TDI Bypass Path
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Solution Overview
Problem
Current testing methods for partially assembled System-in-Package (SiP) devices are limited in test flexibility and cannot comply with JTAG standards when testing individual IC dies, leading to inefficiencies and increased costs due to low manufacturing yield and difficulty in repairing faulty components during assembly.
Innovation Solution
A method and integrated circuit die design that includes a test access port with a primary and secondary test data input, allowing for the insertion of instructions via the secondary input under specific conditions, enabling partial assembly testing and improving diagnostic capabilities by allowing each die to be tested individually within a multi-die device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multiple die arrangement is tested after completion of manufacture, then the device can be assessed whether it operates within predefined parameters, but the yield is lower and repairs are difficult making the process inefficient and costly
Solution Approach 1:
The patent applies preliminary action by enabling testing of individual IC dies at intermediate stages of assembly before the multi-die device is fully completed and packaged. The test arrangement allows each die to be tested independently on the carrier substrate, identifying faulty dies early in the manufacturing process before they are integrated into the final package, thereby preventing waste of assembly resources and enabling repairs or replacements while the device is still accessible.
2Adaptability or versatility
If each IC die has its own independent test arrangement complying with JTAG constraints individually, then each die can be tested independently, but the aggregate of test arrangements breaches JTAG compliancy rules for a single JTAG device
Solution Approach 1:
The patent introduces an intermediary approach by providing a bypass path that connects the TDI pin directly to the TDO pin of each IC die, allowing test signals to pass through individual dies without interfering with the JTAG compliance of the aggregate multi-die device. This intermediary bypass mechanism enables independent testing of each die while maintaining overall system compliance with JTAG standards, as the bypass path acts as a mediator that isolates individual die test operations from the collective test arrangement constraints.
3Measurement precision
If a SiP is tested after completion, then faulty devices can be identified, but the faulty devices must be discarded increasing the cost of known good devices
Solution Approach 1:
The patent implements preliminary action by enabling fault detection at intermediate assembly stages before the multi-die device is fully packaged. Individual IC dies can be tested independently on the carrier substrate, allowing faulty dies to be identified and replaced while the device is still accessible and repairable. This prevents the waste of entire multi-die assemblies due to single die failures, significantly reducing device loss and improving manufacturing yield.
4Reliability
If the test arrangement focuses on testing a completed modular device, then JTAG compliant testing is achieved, but testing of partially assembled SiP is not facilitated
Solution Approach 1:
The patent applies universality by designing a test arrangement that serves multiple functions: it enables JTAG compliant testing of the completed multi-die device while simultaneously facilitating intermediate testing of individual IC dies during the assembly process. The bypass path and test access mechanism are designed to work at both the individual die level and the aggregate device level, providing versatile testing capability across different stages of manufacturing without compromising JTAG compliance.
Data Source
AI summary
The present invention discloses a method of testing a partially assembled multi-die device (1) by providing a carrier (300) comprising a device-level test data input (12) and a device-level test data output (18); placing a first die on the carrier, the first die having a test access port (100c) comprising a primary test data input (142), a secondary test data input (144) and a test data output (152), the test access port being controlled by a test access port controller (110); communicatively coupling the secondary test data input (144) of the first die to the device-level test data input (12), and the test data output (152) of the first die to the device-level test data output (18); providing the first die with configuration information to bring the first die in a state in which the first die accepts test instructions from its secondary test data input (144); testing the first die, said testing including providing the secondary test data input (144) of the first die with test instructions through the device-level test data input (12); and collecting a test result for the first die on the device-level test data output (18). Consequently, a die of a partially assembled multi-die device such as a System-in-Package may be tested using its integrated boundary scan test architecture.