Multi-Die Transformer Module Layout for Heat and Isolation
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Solution Overview
Problem
Existing isolation devices face challenges in heat dissipation, parasitic effects from bond wires, inductive asymmetry, high electric fields due to die proximity, and spatial design constraints, particularly in power applications.
Innovation Solution
A multi-level substrate design with semiconductor dies positioned on opposing surfaces, using solder bumps instead of bond wires, and vertically separated coils to facilitate heat dissipation, reduce electric fields, and eliminate design challenges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor dies are positioned close together to reduce device size, then spatial design constraints are improved, but high electric fields between dies increase causing harmful effects
Solution Approach 1:
The patent positions semiconductor dies on opposite surfaces of the substrate rather than adjacent on the same surface. This dimensional transition from 2D planar arrangement to 3D vertical arrangement reduces electric field interference while maintaining compact device size, directly resolving the contradiction between miniaturization and electric field harm reduction.
2Ease of manufacture
If bond wires are used to connect dies to transformer, then ease of manufacture is improved, but parasitic effects and inductive asymmetry increase
Solution Approach 1:
The patent removes bond wires from the system entirely by establishing direct solder bump connections between the semiconductor dies and transformer coils. This extraction eliminates the source of parasitic effects and inductive asymmetry while maintaining manufacturing feasibility through standardized soldering processes.
3Length of stationary object
If multiple coils are placed in the same plane to reduce device height, then device profile is improved, but heat dissipation capability deteriorates
Solution Approach 1:
The patent distributes transformer coils across multiple vertical layers rather than confining them to a single plane. This 3D spatial arrangement separates heat-generating elements vertically, improving thermal dissipation pathways while maintaining compact overall device height through layered construction.
4Ease of manufacture
If dies are positioned on the same surface to simplify assembly, then ease of manufacture is improved, but heat dissipation and electric field issues worsen
Solution Approach 1:
The patent positions semiconductor dies on opposite surfaces of the substrate, utilizing the third dimension (vertical spacing) to separate heat-generating and electric field-intensive components. This spatial distribution improves thermal management and reduces electric field interference while maintaining assembly simplicity through standardized opposite-surface mounting procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves improved heat dissipation, operational symmetry, reduced parasitic effects, and thinner device profiles while maintaining effective galvanic isolation.
Implementation Method 1
a first coil in a first layer of the substrate, the first coil having first and second terminals, a second coil in a second layer of the substrate that is vertically distanced from the first layer
Implementation Method 2
coupling a first semiconductor die to a first coil of a multi-layer substrate using first solder bumps
Data Source
AI summary
In examples, an isolation device comprises a multi-level substrate having opposing first and second surfaces. The multi-level substrate includes a first coil in a first layer of the substrate, the first coil having first and second terminals, a second coil in a second layer of the substrate that is vertically distanced from the first layer, the second coil having third and fourth terminals, and a dielectric material covering the first and second coils. The device comprises a first semiconductor die coupled to the first surface and to the first and second terminals, a second semiconductor die coupled to the second surface and to the third and fourth terminals, the second semiconductor die galvanically isolated from the first semiconductor die, conductive terminals coupled to the multi-level substrate, and a mold compound covering the multi-level substrate, the first and second semiconductor dies, and the conductive terminals.