Multi-Die Power Package With Wafer Interconnects for Low Inductance
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Solution Overview
Problem
Existing power semiconductor devices in power converters face challenges in achieving compact designs with low power losses and stray inductances due to separate packaging of components, which leads to inefficiencies in electrical energy conversion and motor driving applications.
Innovation Solution
A package design that integrates a first and second power semiconductor die with a lead frame structure, where the second load terminal of the first die is connected to a common base, and the first load terminal of the second die is connected to the same base, with outside terminals extending for electrical insulation and mechanical coupling to a support, allowing for efficient electrical and mechanical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate packages are used for first and second power semiconductor dies, then ease of manufacture is improved, but device compactness and electrical efficiency deteriorate due to increased stray inductances and power losses
Solution Approach 1:
The patent merges the first and second power semiconductor dies into a single integrated package with a common substrate. The leads from both dies are connected to the same substrate, creating a unified electrical structure that reduces stray inductances and power losses while maintaining manufacturing efficiency through standardized packaging processes.
2Device complexity
If separate packages are used for first and second power semiconductor dies, then device complexity is reduced, but stray inductances and power losses increase
Solution Approach 1:
The patent combines multiple power semiconductor dies and their associated leads into a single integrated package structure. This merging reduces the number of separate packages and connections required, thereby reducing stray inductances and power losses while keeping the device complexity manageable through modular design.
3Ease of manufacture
If separate packages are used for first and second power semiconductor dies, then ease of manufacture is improved, but compactness and electrical efficiency deteriorate due to increased stray inductances
Solution Approach 1:
The patent integrates multiple power semiconductor dies and their leads into a single compact package with a common substrate. This merging achieves compactness by eliminating the need for separate packages and long external connections, while maintaining ease of manufacture through standardized packaging techniques.
4Ease of manufacture
If multiple separate packages are used, then manufacturing simplicity is improved, but power converter efficiency deteriorates due to high stray inductances
Solution Approach 1:
The patent merges multiple power semiconductor dies and their leads into a single integrated package structure. This reduces the number of separate packages that need to be manufactured and assembled, simplifying the manufacturing process while simultaneously reducing stray inductances and power losses through shorter internal connections.
Data Source
AI summary
A method includes providing a processed first wafer having front and back sides and including power semiconductor dies implemented within the wafer by processing its front side, each die having a first load terminal at the front side and a second load terminal at the back side; providing an unprocessed second wafer made of an electrically insulating material and having first and second opposing sides; forming a plurality of recesses within the second wafer; filling the plurality of recesses with a conductive material; forming a stack by attaching, prior or subsequent to filling the recesses, the second wafer to the front side of the first wafer, the conductive material electrically contacting the first load terminals of the power semiconductor dies; and ensuring that the conductive material provides an electrical connection between the first side and the second side of the second wafer.