Multi-die Wafer-Level Test and Assembly Without Individual Die Singulation
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Solution Overview
Problem
Current integrated circuit packaging methods, such as CoWoS®, are complex and costly, involving dicing and reassembly of individual dies onto an interposer, which increases manufacturing yield but requires significant process complexity and cost.
Innovation Solution
A method of fabricating integrated circuit packages from a single wafer without initial dicing, where IC dies are tested to identify good and defective ones, and connectivity layers are added based on test results to form groups of good dies, allowing for selective dicing and packaging, reducing complexity and cost while maintaining yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If comprehensive individual die singulation is performed before packaging, then each die can be independently packaged and tested, but the process complexity and cost increase significantly
Solution Approach 1:
The patent segments the wafer into multiple groups based on test results, where each group contains dies with similar performance characteristics. This allows selective packaging of specific groups while maintaining the wafer structure, avoiding complete individual die singulation. The segmentation is performed after testing to identify which dies should be packaged together based on their electrical characteristics.
Solution Approach 2:
The patent performs electrical testing and grouping of dies before the packaging process. By conducting the tests and determining group assignments in advance, the methodology eliminates the need for subsequent individual die testing and reassignment during packaging. This preliminary classification streamlines the overall process and reduces complexity.
2Reliability
If comprehensive individual die singulation is performed before packaging, then each die can be independently packaged, but the manufacturing cost increases significantly
Solution Approach 1:
The patent merges multiple dies into groups based on their test results and electrical characteristics. By packaging dies in groups rather than individually, the methodology reduces the number of packaging operations required. Dies within each group are packaged together as a unit, sharing common packaging infrastructure and reducing per-die packaging costs while maintaining quality control.
Solution Approach 2:
The patent creates universal packaging units that can accommodate multiple dies with similar characteristics. These standardized groups can be packaged using the same process and packaging structure, regardless of the specific die composition within the group. This universality reduces the need for custom packaging solutions for each individual die, thereby reducing manufacturing costs.
3Device complexity
If connectivity layers are added before testing, then the process is simpler, but defective dies cannot be identified and excluded from groups
Solution Approach 1:
The patent performs electrical testing and determines die group assignments before adding connectivity layers. This preliminary classification ensures that only electrically functional dies are included in packaging groups. The connectivity layers are then added based on these pre-determined groups, simplifying the process while maintaining accurate die selection.
Solution Approach 2:
The patent uses test results as an intermediary to guide the connectivity layer formation process. The test data serves as a mediator that determines which dies should be connected together in groups. This intermediary step ensures that connectivity is established only between functional dies, maintaining reliability while simplifying the overall process by avoiding subsequent rework or retesting.
Data Source
AI summary
Methods and apparatus are described for creating a multi-die package from a wafer without dicing the wafer into individual dies and reassembling the dies on an interposer. One example method generally includes testing a plurality of IC dies disposed on a wafer; disposing one or more connectivity layers above the plurality of IC dies, the one or more connectivity layers comprising one or more electrical conductors configured to connect together two or more of the plurality of dies in each of one or more groups of the IC dies; dicing the wafer having the one or more connectivity layers disposed above the plurality of dies into sets, each set comprising one or more of the plurality of dies, wherein the dicing is based on the one or more groups having IC dies that passed the testing; and packaging at least a portion of the sets of dies.