Multi-Dimensional Clock Gating for Register Files and Low-Power RAMs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock-gating techniques in register files and RAMs face inefficiencies as the power consumption of ICG cells and clock buffers increases disproportionately with memory array size, particularly during write access, and are not scalable in RTL-based designs due to timing issues and functional errors.
Innovation Solution
Implementing a multi-dimensional clock-gating system with a mediate layer of ICG cells and separate pre- and post-decoders to reduce total clock power and eliminate clock buffers, optimizing power management in RTL designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If fine-grain clock gating with ICG cells is implemented on each memory row, then power consumption is reduced for small memory arrays, but power consumption of ICG cells and clock buffers increases disproportionately with memory array size
Solution Approach 1:
The patent segments the memory array into multiple groups of rows, with each group served by a single ICG cell rather than having separate ICG cells for each row. This segmentation reduces the total number of ICG cells from N (where N is the number of memory rows) to approximately sqrt(N), thereby reducing the power consumption and complexity of the clock gating mechanism while maintaining effective power savings.
2Loss of energy
If one ICG cell is activated for write access to a specific row, then that row receives clock signal, but remaining ICG cells and input clock tree still draw clock power
Solution Approach 1:
The patent introduces a hierarchical structure with multiple dimensions of clock gating. Instead of a single level where each row has its own ICG cell, the system uses a two-level hierarchy where first-level ICG cells group multiple second-level ICG cells. This dimensional change allows the system to reduce power consumption by disabling entire groups of ICG cells at the first level when only a subset of rows needs clock signals, rather than having to keep the clock tree and all ICG cells powered on.
3Loss of energy
If SRAM custom design flow uses two-level address decoding with AND gates, then efficient power management is achieved, but RTL-based designs cannot directly adopt this approach due to glitches in clock tree and timing issues
Solution Approach 1:
The patent introduces a mediate layer of ICG cells between the pre-decoder and post-decoder layers. This intermediary layer serves as a buffer that isolates the clock tree from the decoding logic, preventing glitches from propagating back to the clock tree. The mediate ICG cells receive gated clock signals from the pre-decoder and distribute them to post-decoder ICG cells, thereby enabling efficient power management while maintaining functional integrity in RTL-based designs.
4Loss of energy
If multi-dimensional clock gating with mediate layer is implemented, then total clock power is reduced and clock buffers are eliminated, but device complexity increases
Solution Approach 1:
The patent makes the ICG cells universal by enabling them to function at multiple levels of the hierarchy. The same ICG cell type serves both as a first-level cell grouping multiple rows and as a second-level cell grouping individual rows. This multi-functionality reduces the need for different types of gating components, thereby reducing overall device complexity while achieving multi-dimensional clock gating and significant power reductions.
Data Source
AI summary
A method and device are provided in which at least a first portion of a write address bus comprising a write address from a write command is received at a first decoder of a memory device, wherein the memory device comprises a set of memory cell rows corresponding to a subset of write addresses from write commands. A first clock signal is received at a first primary integrated clock gating (ICG) cell of the memory device. The first primary ICG cell is configured to provide a first gated clock signal to a first subcircuit of the memory device, including a first non-empty proper subset of the memory cell rows, wherein the first non-empty proper subset includes a plurality of memory cell rows. The first decoder enables or disables the first primary ICG cell, when the write address is in the subset of the write addresses, based on whether the write address corresponds to any memory cell row in the first non-empty proper subset of the memory cell rows, disabling the first primary ICG cell when the write address corresponds to a memory cell row in the set of the memory cell rows but not in the first non-empty proper subset.