Multi-Directional Fin Structure for Parasitic Capacitance Reduction
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Solution Overview
Problem
Miniaturized 3D semiconductor devices face performance degradation and failure due to increased parasitic capacitance and short failures between interconnects, which are not adequately addressed by existing technologies.
Innovation Solution
The semiconductor device incorporates a substrate with first and second fin structures, source/drain regions, and a gate structure, where the second fin region extends in a direction different from the first fin region, allowing the first contact to shift and reduce overlap with the second contact, thereby minimizing parasitic capacitance and preventing short failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the fin structure is miniaturized to increase device density, then device integration is improved, but parasitic capacitance between interconnects increases causing performance degradation
Solution Approach 1:
The patent introduces a multi-directional fin structure where second fin regions extend in a direction different from the first fin regions (e.g., perpendicular or at an angle). This dimensional change in fin orientation allows contact structures to be positioned such that they reduce overlapping areas, thereby minimizing parasitic capacitance while maintaining high device density through the three-dimensional fin architecture.
Solution Approach 2:
The patent employs asymmetric fin structures where the second fin regions are configured with different orientations and positions relative to the first fin regions. This asymmetry enables optimized spacing and positioning of contact structures, reducing the overlapping area between conductive interconnects and thus lowering parasitic capacitance effects in the miniaturized device.
2Length of moving object
If the critical dimensions are decreased to achieve miniaturization, then device scaling is improved, but short failure between interconnects increases causing device failure
Solution Approach 1:
By extending second fin regions in a direction different from the first fin regions, the patent creates additional spatial separation between interconnect structures. This multi-directional approach increases the physical distance between adjacent contacts and interconnects, reducing the risk of short failures even as critical dimensions are scaled down to achieve miniaturization.
Solution Approach 2:
The second fin regions act as intermediary structures that provide additional spacing and isolation between the first fin regions and associated interconnects. This intermediary fin structure helps prevent direct contact or bridging between adjacent interconnect elements, thereby reducing short failure risks in miniaturized devices.
3Reliability
If contact structures are positioned to connect source/drain regions, then electrical connection is improved, but overlapping area with gate contact increases causing parasitic capacitance
Solution Approach 1:
The patent positions contact structures to connect source/drain regions on the first fin regions while simultaneously extending second fin regions in a different direction to reduce the overlapping area between these contacts and the gate contact. This multi-directional configuration maintains necessary electrical connections while minimizing parasitic capacitance through reduced spatial overlap.
Data Source
AI summary
A semiconductor device includes a substrate, a fin structure protruding from the substrate in a direction perpendicular to an upper surface of the substrate, the fin structure including first fin regions extending in a first direction and second fin regions extending in a second direction different from the first direction, source/drain regions disposed on the fin structure, a gate structure intersecting the fin structure, a first contact connected to one of the source/drain regions, and a second contact connected to the gate structure and being between the second fin regions in plan view.