Multi-DLL Clock Synchronization for Wide Frequency Range
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Solution Overview
Problem
Conventional delay locked loop (DLL) circuits have a limited operating frequency range due to the complexity of transistor chains and long lock-in periods, which restricts the frequency range over which high-speed electronic systems can operate effectively.
Innovation Solution
The solution involves combining multiple DLLs with different frequency ranges and a selection mechanism to choose the appropriate DLL based on the desired operating frequency, using a selector and a selection control mechanism that can be implemented through various means such as pin inputs, register contents, or frequency detection, allowing for extended frequency operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single DLL circuit is designed to cover a wide frequency range, then the frequency range is extended, but the transistor chain complexity and lock-in period increase significantly
Solution Approach 1:
The patent divides a single wide-range DLL into multiple separate DLL circuits, each optimized for a specific frequency subrange. Each DLL has its own phase detector, delay chain, and control logic tailored to its designated range, avoiding the complexity of a single universal DLL while collectively covering the entire desired frequency spectrum.
2Adaptability or versatility
If a single DLL circuit is designed to cover a wide frequency range, then the frequency range is extended, but the lock-in period increases significantly
Solution Approach 1:
By segmenting the frequency range into multiple DLLs, each DLL can be optimized for rapid acquisition within its specific range. The selection mechanism quickly identifies the appropriate DLL based on the desired frequency, avoiding the long lock-in period that would occur in a single DLL attempting to cover the entire range.
Solution Approach 2:
The system performs preliminary frequency detection or selection before activating the appropriate DLL. This preliminary action identifies which DLL should be used, allowing the system to start with the correct circuit immediately rather than requiring a lengthy lock-in period to adapt to the frequency range.
3Adaptability or versatility
If multiple DLLs are used to extend frequency range, then the frequency range is expanded, but the device complexity increases due to selection mechanism
Solution Approach 1:
The selection mechanism is designed to automatically detect the desired operating frequency and select the appropriate DLL without external intervention. The system self-manages the selection process through frequency detection circuits or predefined range mappings, minimizing the complexity burden on the user while maintaining multiple DLLs for extended frequency coverage.
Data Source
AI summary
A delay locked loop (DLL) circuit having an expanded operating frequency range is achieved by providing multiple DLLs, each having a different range of operating frequencies. A selection mechanism selects the DLL with the appropriate operating frequency range. The output of the selected DLL is used as the output of the delay locked loop circuit and is fed back to the input of the selected DLL so as to achieve phase lock with an input signal. The selection mechanism can operate in accordance with, among other things, a metallization mask option, the state of one or more pins, the state of one or more bits of a software accessible register or storage device, or the output of a frequency detector which detects the frequency of the input clock signal. The selection mechanism can also cause the selected DLL to be activated and the unselected DLL(s) to be deactivated, thereby conserving power.