Multi-Domain Network Timestamping with PHY Delay Compensation
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Solution Overview
Problem
Network devices with multiple synchronization domains face challenges in implementing timestamping at network interfaces due to the need for multiple clocks, which complicates internal communication mechanisms, increases cost, power consumption, and physical size.
Innovation Solution
A network device uses a local-domain clock and a domain-specific clock to timestamp packets, with the local-domain clock calculating internal delays and the domain-specific clock generating accurate timestamps without requiring multiple clocks at each interface, reducing internal communication demands and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple domain-specific clocks are provided to each network interface for timestamping in multiple synchronization domains, then timestamping accuracy is improved, but device complexity and internal communication requirements increase
Solution Approach 1:
The patent segments the timestamping function into two parts: the PHY processor generates a local timestamp using a single local-domain clock, and the packet processor generates a domain-specific timestamp using domain-specific clocks. This segmentation allows each processor to use only the clocks it needs, reducing the complexity of clock distribution while maintaining timestamping accuracy for multiple synchronization domains.
Solution Approach 2:
The packet processor acts as an intermediary that receives the local timestamp from the PHY processor and combines it with domain-specific timestamps. This intermediary approach allows the system to maintain accurate timestamps for multiple domains without requiring the PHY processor to have direct access to multiple domain-specific clocks, thereby reducing internal communication complexity.
2Adaptability or versatility
If multiple domain-specific clocks are distributed to each network interface, then timestamping capability is improved, but manufacturing cost increases
Solution Approach 1:
The local-domain clock serves multiple functions: it provides timing for the PHY processor and enables the generation of local timestamps that can be combined with domain-specific timestamps. This universal use of the local-domain clock reduces the need for multiple specialized clocks at each interface, thereby lowering manufacturing costs while maintaining versatile timestamping capability.
Solution Approach 2:
The patent merges the timestamping functions of the PHY processor and packet processor, where the PHY processor generates local timestamps and the packet processor generates domain-specific timestamps. This combining of functions allows the system to achieve multi-domain timestamping capability without requiring each interface to have multiple domain-specific clocks, reducing manufacturing complexity and cost.
3Measurement precision
If multiple domain-specific clocks are provided to each interface, then timestamping precision is improved, but power consumption increases
Solution Approach 1:
The patent segments the clock usage such that the PHY processor uses only the local-domain clock while the packet processor uses domain-specific clocks. This segmentation reduces the total number of active clocks at each interface, thereby reducing power consumption while maintaining timestamping precision through the coordinated use of timestamps from both processors.
Solution Approach 2:
The PHY processor generates its own local timestamp using the local-domain clock without requiring domain-specific clocks, making the system more energy-efficient. This self-service approach allows the PHY processor to perform timestamping independently with minimal clock resources, reducing overall power consumption while maintaining precision.
Data Source
AI summary
A physical layer (PHY) processor of a network device receives a timing message via an external network and generates a first timestamp using a first local-domain clock used by the PHY processor. The PHY processor transfers the timing message and the first timestamp to a packet processor of the network device via an internal communication link. The packet processor generates a second timestamp for the timing message using a domain-specific clock. The packet processor determines a delay value using the first timestamp, the delay value accounting for a time delay corresponding to the transfer of the timing message within the network device from the PHY processor to the packet processor. The packet processor adjusts the second timestamp using the delay value to generate an adjusted domain-specific timestamp for the timing message.