Multi-Domain Vertical Alignment Pixel Structure Lateral Etched Groove

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The multi-domain vertical alignment (MVA) pixel structure faces issues with ITO residue during fabrication, leading to electrical connectivity between the first and second pixel electrodes, resulting in poor display performance.

Innovation Solution

A fabrication method that includes forming a lateral etched groove on the sidewall of a trench in the insulating and passivation layers, ensuring electrical insulation between the first and second pixel electrodes, and using a semiconductor layer with a higher etching rate to expose the side edge, preventing residue-induced connectivity issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional fabrication process is used to form pixel electrodes, then the manufacturing process is simple, but ITO residue causes electrical connectivity between first and second pixel electrodes, resulting in poor display performance

Engineering Contradiction:
Improveelectrical insulation between pixel electrodesVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming the lateral etched groove in the passivation layer before depositing the pixel electrodes. This pre-formed groove creates a physical barrier that prevents ITO residue from causing electrical connectivity between adjacent pixel electrodes, ensuring reliable electrical insulation is established before the electrode formation process begins.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies segmentation by dividing the passivation layer into distinct regions separated by lateral etched grooves. These grooves segment the continuous passivation layer into isolated sections, each supporting a pixel electrode, thereby preventing residue-induced connectivity between adjacent electrodes through the segmented structure.

Inventive Principle:
Principle #1Segmentation

2Reliability

If additional lateral etched groove formation steps are added to ensure electrical insulation, then display performance and reliability improve, but manufacturing complexity and production time increase

Engineering Contradiction:
Improveproduction yield rateVSAvoidproduction yield rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges the formation of lateral etched grooves with the existing passivation layer deposition process. By integrating the groove formation into the passivation layer fabrication sequence rather than adding completely separate processing steps, the method achieves improved reliability while minimizing the impact on production throughput and manufacturing complexity.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively advances the production yield rate and improves the reliability of the MVA pixel structure by ensuring electrical insulation between the electrodes, enhancing display performance.

Implementation Method 1

there is a trench in the insulating layer and the passivation layer, and a lateral etched groove is located on a sidewall of the trench. The lateral etched groove exposes the side edge of the semiconductor layer

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS7811869B2Fabrication method of multi-domain vertical alignment pixel structure
Publication Date: 2010.10.12 OPTRONIC SCIENCES LLC
  • US7811869B2 patent drawing
  • US7811869B2 patent drawing
  • US7811869B2 patent drawing

AI summary

A fabrication method of a multi-domain vertical alignment pixel structure includes providing a substrate, forming a gate on the substrate, and forming an insulating layer on the substrate. A channel layer and a semiconductor layer are formed on the insulating layer. A source, a drain, and a capacitor-coupling electrode are formed. A passivation layer is formed to cover the source, the drain, a part of the channel layer, and a part of the semiconductor layer. A via hole is formed in the passivation layer to expose the drain, and a trench is formed in the passivation layer and the insulating layer. A lateral etched groove on the sidewall of the trench is formed to expose the side edge of the semiconductor layer. A first pixel electrode and a second pixel electrode are formed on the passivation layer at both sides of the trench, respectively.