Multi-dot Flash Memory Asymmetrical Floating Gates
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Solution Overview
Problem
Current NAND flash memory technologies face challenges in miniaturization due to intercell interference and reliability issues with tunnel insulating films, leading to reduced storage capacity and increased production costs, especially when attempting to implement quantum dot technology for next-generation memory solutions.
Innovation Solution
A multi-dot flash memory architecture is developed with separately provided gate and tunnel insulating films, utilizing a side-wall spacer lithography process to create floating gates with asymmetrical side surfaces, allowing for efficient charge injection and emission by alternating the roles of tunnel insulating films during writing and erasing, thereby enhancing reliability and reducing production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the tunnel insulating film is thinned to reduce intercell interference, then the interference effect between adjacent floating gates is reduced, but charge traps are generated in the tunnel insulating film during writing and erasing, reducing reliability
Solution Approach 1:
The patent divides the single tunnel insulating film into two separate tunnel insulating films positioned on opposite sides of the floating gate. This segmentation allows each film to be independently optimized and prevents charge traps generated in one film from affecting the other film's tunneling performance, thereby maintaining reliability while enabling thinning to reduce interference.
Solution Approach 2:
The patent extracts the charge trap generation problem from the gate insulating film by providing separate tunnel insulating films for writing and erasing operations. This extraction allows the gate insulating film to be optimized for transistor characteristics without being degraded by charge traps, separating the functions of charge injection and threshold voltage control.
2Area of moving object
If lateral shrinkage is implemented to miniaturize the memory cell, then the cell size is reduced, but the tunnel insulating film becomes thinner and more susceptible to charge trap generation
Solution Approach 1:
By segmenting the tunnel insulating film into two separate films, the patent enables further lateral shrinkage of the memory cell without compromising reliability. Each thin tunnel insulating film can be optimized for its specific function (writing or erasing), allowing miniaturization while maintaining adequate film thickness for reliable operation.
Solution Approach 2:
The patent transitions from a single-plane tunnel insulating film structure to a three-dimensional structure with tunnel insulating films on both sides of the floating gate. This dimensional change allows the memory cell to be miniaturized in the lateral plane while maintaining sufficient tunneling path integrity through the vertical arrangement of the dual tunnel films.
3Device complexity
If the same tunnel insulating film is used for both writing and erasing, then the structure is simple, but charge traps accumulate and reduce the threshold window between writing and erasing states
Solution Approach 1:
The patent segments the tunnel insulating film function into two separate physical films: one dedicated to writing (charge injection) and another dedicated to erasing (charge removal). This segmentation prevents charge trap accumulation from affecting both operations, maintaining a stable threshold window despite the increased structural complexity.
Solution Approach 2:
The patent applies local quality by optimizing each tunnel insulating film for its specific function. The writing-side tunnel film is optimized for efficient charge injection, while the erasing-side tunnel film is optimized for charge removal, with each film's thickness and material properties tailored to its local role, thereby maintaining overall system reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability of tunnel insulating films, maintains the threshold voltage stability, and enables the storage of multiple bits in a single memory cell, facilitating the miniaturization of memory cells while reducing production costs and increasing storage capacity.
Implementation Method 1
a tunnel insulating film used at the time of writing/erasing
Implementation Method 2
a tunnel insulating film used at the time of writing/erasing
Data Source
AI summary
A multi-dot flash memory includes active areas arranged in a first direction, which extend to a second direction crossed to the first direction, the first and second direction being parallel to a surface of a semiconductor substrate, floating gates arranged in the first direction, which are provided above the active areas, a word line provided above the floating gates, which extends to the first direction, and bit lines provided between the floating gates, which extend to the second direction. Each of the floating gates has two side surfaces in the first direction, shapes of the two side surfaces are different from each other, and shapes of the facing surfaces of the floating gates which are adjacent to each other in the first direction are symmetrical.