Multi-ECC Memory Architecture for High-Capacity Error Correction

Solution Overview

Problem

As memory capacity increases, it becomes challenging to fabricate error-free memory systems, and existing error correction methods in semiconductor memory systems are inefficient, particularly due to inferior error detection and correction capabilities in memory error correction circuits compared to system error correction circuits.

Innovation Solution

A memory system is designed with a memory controller and memory that generate and utilize multiple error correction codes, including a system error correction code and a memory error correction code, to enhance error correction efficiency by improving the error detection and correction capabilities of the memory error correction circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory capacity is increased, then storage capability is improved, but fabrication difficulty increases and error-free memory cells become harder to produce

Engineering Contradiction:

Improvememory capacityVSAvoiderror-free fabrication

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The error correction function is segmented into two independent circuits: a system error correction circuit in the memory controller and a memory error correction circuit in the memory device. Each circuit generates and processes separate error correction codes (system ECC and memory ECC), allowing independent optimization of each correction mechanism to handle different error types and locations effectively.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Error correction codes are generated in advance during the write operation before data is stored. The system error correction circuit generates system ECC codes, and the memory error correction circuit generates memory ECC codes, both of which are stored alongside the data. This preliminary action ensures that correction capabilities are ready before read operations occur, enabling rapid error correction without delaying data access.

Inventive Principle:

Principle #10Preliminary action

2Device complexity

If existing single error correction method is used, then device complexity is reduced, but error correction efficiency and detection capability are insufficient

Engineering Contradiction:

Improveerror correction structureVSAvoiderror correction efficiency

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The error correction function is segmented into two independent circuits: a system error correction circuit in the memory controller and a memory error correction circuit in the memory device. Each circuit generates and processes separate error correction codes (system ECC and memory ECC), allowing independent optimization of each correction mechanism to handle different error types and locations effectively.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent combines two error correction mechanisms (system ECC and memory ECC) into a unified error correction framework. Both correction codes are generated, stored, and processed together during read operations, merging their capabilities to provide comprehensive error detection and correction that neither circuit could achieve alone, thereby improving overall reliability without excessive complexity.

Inventive Principle:

Principle #5Merging (Combining)

3Ease of manufacture

If memory error correction circuit capabilities are inferior to system error correction circuit, then manufacturing is easier, but error detection and correction effectiveness is reduced

Engineering Contradiction:

Improvememory device fabricationVSAvoiderror detection capability

Core Design Contradiction:

Ease of manufactureVSMeasurement precision

Solution Approach 1:

The error correction function is segmented into two independent circuits: a system error correction circuit in the memory controller and a memory error correction circuit in the memory device. Each circuit generates and processes separate error correction codes (system ECC and memory ECC), allowing independent optimization of each correction mechanism to handle different error types and locations effectively.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the parameters of error correction by implementing different correction capabilities in different locations. The system error correction circuit uses one set of correction parameters while the memory error correction circuit uses optimized parameters tailored to memory-specific errors. This parameter differentiation allows each circuit to be manufactured with appropriate complexity while maximizing overall error detection and correction effectiveness.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10901842B2Memory system and operating method thereof

Publication Date: 2021.01.26 SK HYNIX INC

AI summary

A memory system includes a memory controller including: a system error correction code generation circuit configured to generate a first system error correction code based on write data, and generate a second system error correction code based on the write data and the first system error correction code; and a memory including: a memory error correction code generation circuit configured to generate a memory error correction code based on the write data and the first system error correction code transferred from the memory controller; and a memory core configured to store the write data, the first system error correction code, the second system error correction code and the memory error correction code.