Multi-Emitter Bandgap Reference Circuit for Low Drift
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Solution Overview
Problem
Conventional bandgap reference voltage circuits experience mechanical stress-induced temperature drift and lifetime drift due to packaging inaccuracies, leading to variations in base-emitter voltages and output voltages.
Innovation Solution
A bandgap reference circuit with a multi-emitter transistor configuration that minimizes surface area, reducing mechanical stress by arranging 9 emitters in an 8:1 ratio around a central emitter, resulting in a smaller ΔVbe cell area and decreased lifetime drift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional plastic packaging is used for reference voltage circuits, then the circuit can be manufactured and packaged, but mechanical stress causes temperature drift and lifetime drift due to packaging-induced inaccuracies
Solution Approach 1:
The patent segments the transistor emitter structure into multiple discrete emitters (8:1 ratio) arranged in a specific geometric pattern. This segmentation allows the circuit to compensate for mechanical stress effects by having multiple emitters that experience slightly different stresses, and by taking the average or differential effect, the overall reference voltage stability is improved despite packaging-induced mechanical stress
Solution Approach 2:
The patent changes the physical parameters of the transistor emitters by creating an 8:1 emitter area ratio with specific geometric arrangement. This parameter change enables the circuit to be less sensitive to mechanical stress variations, as the differential base-emitter voltages from emitters of different areas can be combined to cancel out stress-induced drift effects
2Ease of manufacture
If the ΔVbe cell surface area is large, then the circuit layout is simpler, but mechanical stress causes local variations over the chip area leading to drift in base-emitter voltages
Solution Approach 1:
The patent divides the ΔVbe cell into multiple segmented emitters (8:1 configuration) rather than using a single large emitter. This segmentation allows the cell to maintain a compact layout while reducing the impact of mechanical stress gradients across the chip, as each small emitter experiences more uniform stress conditions
Solution Approach 2:
The patent applies local quality by creating emitters with different areas (8:1 ratio) at specific locations within the ΔVbe cell. This local variation in emitter quality enables the circuit to compensate for spatial variations in mechanical stress across the chip area, improving voltage accuracy despite stress gradients
3Reliability
If multiple separate NPN transistors are used to achieve the 8:1 emitter ratio, then the circuit can be implemented, but the surface area and device complexity increase
Solution Approach 1:
The patent merges multiple emitter functions into a single multi-emitter transistor structure. Instead of using separate transistors for each emitter, the invention combines 8 emitters of one area and 1 emitter of another area into a single integrated transistor, achieving the 8:1 ratio functionality while minimizing surface area and reducing the number of discrete components
Solution Approach 2:
The patent employs a nested arrangement where emitters of different sizes are positioned in a hierarchical pattern (larger emitter surrounded by or positioned relative to smaller emitters). This nesting approach optimizes the spatial arrangement to minimize the overall ΔVbe cell area while maintaining the required 8:1 emitter area ratio for accurate voltage reference
Data Source
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AI summary
A bandgap voltage reference circuit comprises a plurality of delta base-emitter voltage (ΔVbe) cells extending between first and second voltage rails in a serial arrangement. Each ΔVbe cell includes a transistor comprising a single first emitter connection and eight second emitter connections. The single first emitter connection of a second transistor in the serial arrangement is coupled to one of the eight second emitter connections of a first transistor in the serial arrangement, and one of the eight second emitter connections of the second transistor is coupled to the single first emitter connection of a third transistor in the serial arrangement to form an electrical path from the first transistor to the third transistor. A resistor is at a distal end of the serial arrangement. An output voltage across the resistor includes a sum of delta base-emitter voltages generated by the plurality of ΔVbe cells.