Multi-Enabled Clock Gating Circuit Reducing Setup Time
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Solution Overview
Problem
Conventional multi-enabled clock gating circuits introduce additional signal propagation delay in clock enable signals, increasing setup time and affecting the maximum attainable operating frequency of integrated circuits, particularly during normal operation.
Innovation Solution
A multi-enabled clock gating circuit utilizing an or-and-invert (OAI) logic gate and clock enable control circuit, which generates a gated clock signal by inverting an input clock signal responsive to active timing-sensitive or timing-insensitive clock enable signals, and prevents the timing-insensitive signal from affecting the OAI logic gate when the timing-sensitive signal is active, thereby reducing setup time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional clock enable selection mechanisms (multiplexer or combinatorial logic) are used to select among multiple clock enable signals, then the circuit can handle multiple clock enable signals for different applications, but additional signal propagation delay is introduced to the clock enable signal paths
Solution Approach 1:
The patent segments the clock enable signals into two distinct categories: timing-sensitive clock enable signals and timing-insensitive clock enable signals. This segmentation allows different handling paths for different signal types, eliminating the need for a universal multiplexer that introduces delay to all signals. The timing-sensitive signals bypass the selection mechanism entirely, while timing-insensitive signals are routed through it, thus resolving the contradiction between multi-enabled capability and setup time requirements.
2Reliability
If increased setup time is provided for clock enable signals to reduce clock-gating induced skew, then signal skew is reduced, but the maximum attainable operating frequency of the IC decreases
Solution Approach 1:
The patent applies local quality by providing different path characteristics for different types of clock enable signals. Timing-sensitive signals receive a direct path with minimal delay to ensure proper timing and reduce skew, while timing-insensitive signals can tolerate the delay introduced by the selection mechanism. This localized optimization allows the circuit to maintain high operating frequencies for critical timing-sensitive operations while still supporting multiple clock enable functions.
Data Source
AI summary
A multi-enabled clock gating circuit reduces clock enable setup time. In one example, the multi-enabled clock gating circuit comprises an OAI logic gate and a clock enable control circuit. The OAI logic gate is configured to generate a gated clock signal by inverting an input clock signal responsive to one of a timing-sensitive clock enable signal and a timing-insensitive clock enable signal being active. The clock enable control circuit is configured to prevent the OAI logic gate from receiving the timing-insensitive clock enable signal responsive to the timing-sensitive clock enable signal being active. In one or more embodiments, a multi-enabled clock gating circuit having reduced clock enable setup time may be included in an integrated circuit for implementing clock gating during different operating modes of the integrated circuit.