Multi-Engine FPGA Synthesis Partitioning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current FPGA synthesis tools often generate inefficient circuit configurations, leading to larger designs and timing issues, as they struggle to optimize circuit components from high-level logic functions, resulting in the need for more resources and potential performance problems.
Innovation Solution
The method involves using multiple synthesis engine configurations to partition and optimize circuit designs, selecting the most suitable engines based on criteria like timing, power, and area, and combining their results to generate a more efficient gate-level netlist.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single synthesis tool is used, then the synthesis process is simple and fast, but the circuit configuration efficiency is poor and produces larger designs
Solution Approach 1:
The patent divides the circuit design into multiple sections and applies different synthesis engine configurations to each section. The synthesis tool partitions the HDL design, selects appropriate synthesis engines for each partition based on criteria like timing, area, or power, and combines the results. This segmentation allows each section to be optimized by the most suitable synthesis engine rather than using a single engine for the entire design, thereby improving overall configuration efficiency.
Solution Approach 2:
The synthesis tool is designed to support multiple synthesis engine configurations within a single unified platform. It can select from different synthesis engines (e.g., timing-optimized, area-optimized, power-optimized) and combine their results. This multi-functionality allows the tool to achieve the benefits of multiple specialized synthesis engines without requiring separate tools for each optimization goal, thus improving productivity while managing complexity through integration.
2Quantity of substance
If multiple synthesis engine configurations are used, then circuit configuration efficiency is improved and design size is reduced, but the synthesis process becomes more complex
Solution Approach 1:
The patent partitions the circuit design into multiple sections and applies different synthesis engine configurations to each section. The synthesis tool partitions the HDL design, selects appropriate synthesis engines for each partition based on criteria like timing, area, or power, and combines the results. This segmentation allows each section to be optimized by the most suitable synthesis engine rather than using a single engine for the entire design, thereby improving overall configuration efficiency.
Solution Approach 2:
The synthesis tool changes parameters such as optimization goals (timing, area, power) and engine selection criteria to generate different circuit configurations. By varying these parameters across different synthesis runs or partitions, the tool can explore multiple design spaces and select configurations that use fewer FPGA resources. The parameter changes enable the system to trade off between different optimization criteria to achieve more efficient resource utilization.
3Reliability
If a single synthesis engine is used, then the synthesis process is fast, but timing performance may be poor
Solution Approach 1:
The patent divides the circuit design into multiple sections and applies different synthesis engine configurations to each section. The synthesis tool partitions the HDL design, selects appropriate synthesis engines for each partition based on criteria like timing, area, or power, and combines the results. This segmentation allows each section to be optimized by the most suitable synthesis engine rather than using a single engine for the entire design, thereby improving overall configuration efficiency.
Solution Approach 2:
Instead of using a single synthesis engine for the entire design, the patent applies multiple synthesis engines to different portions of the design. This partial action approach allows timing-critical sections to be synthesized with timing-optimized engines while other sections use engines optimized for different criteria. The synthesis tool can then combine these partial results to achieve overall timing performance that would not be possible with a single engine applied to the complete design.
Data Source
AI summary
Disclosed herein are representative embodiments of methods, systems, and apparatus for performing synthesis. For example, in one exemplary method disclosed herein, a high-level description of a complete circuit design is partitioned into a plurality of sections. Two or more synthesis engine configurations are selected for a respective one of the sections. The respective one of the sections is synthesized using the two or more selected synthesis engine configurations, thereby generating two or more gate-level descriptions. A gate-level description of the complete circuit design is generated that includes at least a portion of one of the gate-level descriptions. Computer-readable media storing instructions for causing a computer to perform any of the disclosed methods are also disclosed herein.