Multi-Fabric Interference Reduction in Electronic Design
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Solution Overview
Problem
Conventional electronic design approaches fail to effectively manage interferences and disturbances in multi-fabric designs, particularly due to the inability to handle scale differences and complex geometries, leading to inefficiencies and potential design failures in integrated circuits, packaging, and printed circuit boards.
Innovation Solution
A method and system that identify and annotate loops in multi-fabric electronic designs, determine critical circuit components affected by these loops, and trigger remedial actions to reduce or eliminate negative impacts, using connectivity analysis and topology construction to optimize design fabrics across multiple hierarchies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional EM analyses model geometries with high precision using polygonal approximations, then measurement precision is improved, but productivity deteriorates due to prohibitively long computation time for full-chip analyses
Solution Approach 1:
The patent segments the electronic design into multiple hierarchical levels (device level, circuit level, package level, board level). At each level, only relevant components and geometries are modeled with high precision using polygonal approximations, while other areas use simplified representations. This segmentation allows EM analysis to focus computational resources on critical regions, maintaining measurement precision for important geometries while improving overall productivity by avoiding full-chip high-precision modeling.
2Reliability
If conventional approaches perform full-chip EM analyses with high-precision geometric modeling, then reliability of interference detection is improved, but loss of time increases making the approach infeasible for modern integrated circuits
Solution Approach 1:
The patent performs preliminary actions by conducting EM analyses at lower hierarchical levels (device level, circuit level) before proceeding to higher levels (package level, board level). This preliminary analysis identifies critical interference patterns and problematic geometries early in the design process. Subsequent higher-level analyses then focus specifically on these identified problem areas, maintaining reliable interference detection while significantly reducing total analysis time compared to performing full-chip high-precision EM analysis from scratch.
3Productivity
If chip-level placement decisions are made independently without considering downstream fabrics, then device placement optimization is improved, but object-generated harmful factors increase due to excessive coupling and complex routing in package and PCB substrates
Solution Approach 1:
The patent implements a multi-fabric EM analysis system that simultaneously considers multiple design fabrics (chip fabric, package fabric, PCB fabric) across different hierarchical levels. The analysis framework is universal and can evaluate electromagnetic interactions at any combination of these levels. This allows device placement decisions to be optimized with awareness of downstream fabric constraints and characteristics, reducing excessive coupling and routing complexity in package and PCB substrates while maintaining placement efficiency through automated multi-level evaluation.
Data Source
AI summary
Disclosed are methods, systems, and articles of manufacture for reducing interferences and disturbances in a multi-fabric electronic design. These techniques identify connectivity for an electronic design that includes design data in multiple design fabrics. One or more interference modules are executed to detect a loop in the electronic design with at least the connectivity. These techniques further execute the one or more interference reduction modules to determine at least one critical circuit component upon which the loop exerts a negative impact. One or more remedial actions are then triggered to reduce or eliminate the negative impact on the critical circuit component design.