Power FET Current Measurement With Multi-FET Dynamic Matching
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Solution Overview
Problem
Existing methods for measuring power current delivered by a power FET transistor face issues such as dynamic behavior differences and response variations due to edge effects and temperature changes, especially in transistors with small dimensions.
Innovation Solution
A device comprising a current-measuring power FET and additional FET transistors configured to divide and measure the current, with optimized semiconductor areas and channel widths to maintain consistent performance across varying temperatures and conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a smaller measurement FET is used to ensure low measurement current, then the current measurement capability is improved, but dynamic behavior differences and response variations occur due to edge effects and temperature changes
Solution Approach 1:
The patent divides the measurement function into multiple FET transistors (first FET, second FET, and measurement FET) rather than using a single small measurement FET. This segmentation allows the system to achieve low measurement current through the combined action of multiple devices, avoiding the edge effects and dynamic behavior issues that plague single small FETs while maintaining measurement precision.
Solution Approach 2:
The patent introduces intermediate FET transistors (first and second FETs) that act as mediators between the main power FET and the measurement circuit. These intermediary FETs buffer and condition the signal, allowing accurate measurement of low currents without exposing the measurement FET to the harsh conditions (high voltage, high current, temperature variations) that cause dynamic behavior discrepancies.
2Measurement precision
If the semiconductor area of the measurement FET is significantly reduced, then the measurement current is kept very low, but edge effects and corner cell variations degrade measurement accuracy
Solution Approach 1:
The patent merges multiple FET transistors (measurement FET, first FET, second FET) into a unified measurement circuit architecture. By combining these devices, the system achieves the equivalent measurement capability of a large FET while using physically smaller components, thereby avoiding edge effects and manufacturing variations that would affect a single small measurement FET.
Solution Approach 2:
The patent changes the architectural parameters of the measurement circuit from a single FET design to a multi-FET configuration. This parameter change allows the system to achieve the desired measurement current level without relying on reducing the area of a single measurement FET, thus avoiding the manufacturing precision issues associated with small transistor dimensions.
3Reliability
If a larger power FET is used for current measurement, then dynamic behavior matches the main power FET better, but the measurement current becomes too high for accurate measurement
Solution Approach 1:
The patent transitions from a one-dimensional solution (single FET size) to a multi-dimensional architecture involving multiple FETs of different sizes working together. The measurement FET can be small for low measurement current, while the first and second FETs provide the necessary current buffering and scaling, achieving both low measurement current and good dynamic behavior matching without contradiction.
Data Source
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AI summary
This description relates to a device (100) for measuring a power current delivered by a main power FET (102), comprising: - a current-measuring power FET (110) coupled to the main FET; - first and second FETs (114, 116) whose gates are coupled together, the first FET being coupled to the current-measuring FET, in which a source/drain electrode (122) of the second FET is coupled to a source/drain electrode (118) of the first FET, or a source/drain electrode (122) of the second FET is coupled to a source/drain electrode (108) of the main FET or to a voltage source or load external to the device, and source/drain electrodes (124, 126) of the first and second FETs are coupled together.