Multi-FET Semiconductor Package Layout for Lower Impedance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packages for CPUs and GPUs are large in size and have high impedance due to the inclusion of multiple driver metal-oxide-semiconductors (DrMOSs), which occupy space and increase electrical resistance.
Innovation Solution
A semiconductor package design that integrates two or more low side and high side FETs, metal clips, a metal slug, an IC controller, and a molding encapsulation, co-packaged to reduce size and impedance, using a lead frame with etched die paddles and grooves for improved integration and bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple driver metal-oxide-semiconductors (DrMOSs) are included in the semiconductor package, then the power delivery capability is improved, but the package size increases and impedance increases
Solution Approach 1:
The patent combines multiple driver FETs (both low-side and high-side) into a single integrated package with shared common connections. Specifically, multiple low-side FETs share a common source connection and multiple high-side FETs share a common drain connection, merging what would traditionally be separate packages into one unified structure. This merging reduces the overall package size while maintaining the power delivery capability of multiple drivers.
Solution Approach 2:
The semiconductor package implements multi-functionality by enabling multiple FETs to share common electrical connections (common source, common drain, common gate control). This universal sharing of connections allows the package to function as multiple independent driver circuits while using a single package structure, thereby reducing size and impedance compared to separate packages for each driver.
2Power
If multiple driver metal-oxide-semiconductors (DrMOSs) are included in the semiconductor package, then the power delivery capability is improved, but the impedance increases
Solution Approach 1:
By merging multiple FETs into a single package with shared common connections, the patent reduces the total number of external connection points and inter-package traces. This merging eliminates the impedance contributions from separate package substrates and inter-connectors, thereby reducing overall impedance while maintaining multiple driver functionality for improved power delivery.
Solution Approach 2:
The common source and common drain connections act as intermediaries that directly connect multiple FETs without introducing additional impedance from separate packages or trace paths. These shared connections serve as low-impedance pathways that enable multiple drivers to operate simultaneously with reduced overall impedance compared to discrete package configurations.
3Area of stationary object
If the package size is reduced by co-packaging multiple FETs, then the space efficiency is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent segments the package into distinct functional regions: a common source region for multiple low-side FETs, a common drain region for multiple high-side FETs, and separate gate control regions. This segmentation allows each FET to be independently attached and wired to its designated common connection point, simplifying the manufacturing process compared to a fully integrated monolithic structure while still achieving compact packaging.
Solution Approach 2:
The patent utilizes vertical stacking and three-dimensional arrangement of FETs within the package footprint. By attaching FETs to the underside of the package substrate and routing connections through vertical vias and bond wires, the design achieves compact horizontal footprint while managing the complexity of interconnections in the vertical dimension, thereby reducing package area without proportionally increasing manufacturing difficulty.
Data Source
AI summary
A semiconductor package comprises a lead frame, two or more low side field-effect transistors (FETs), two or more high side FETs, two or more metal clips, a metal slug, an integrated circuit (IC) controller, and a molding encapsulation. A method for fabricating a semiconductor package comprising the steps of providing a lead frame comprising die paddles; attaching transistors to the die paddles respectively; mounting metal clips; mounting a metal slug and a controller, applying bonding wires; forming a molding encapsulation; and applying a singulation process.