Multi-Field Plate LDMOS Layout for Wider Voltage Operation
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Solution Overview
Problem
Conventional high-voltage LDMOS devices with two different gate dielectric layer heights have limited operable voltage ranges and performance issues due to oxide quality, affecting device efficiency.
Innovation Solution
A high-voltage device with multi-field plates is developed, featuring a semiconductor layer with well and body regions, a gate, resist protection oxide region, and parallel field plates not directly connected to each other, which are connected to the resist protection oxide region through contact plugs or other conductive structures, reducing electric field gradients and hot carrier injection effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional LDMOS device with two different gate dielectric layer heights is used, then the device structure is simple to manufacture, but the operable voltage range is limited and device performance is affected by oxide quality
Solution Approach 1:
The gate structure is segmented into multiple field plates (first field plate, second field plate, third field plate) with different heights and positions, allowing different regions to operate at different voltages. This segmentation enables the device to handle a wider voltage range while maintaining controlled electric field distribution across the drift region.
Solution Approach 2:
Different field plates are positioned at specific locations (first field plate near source, second field plate above drift region, third field plate near drain) with different heights and doping concentrations, creating locally optimized electric field control. This local quality approach allows tailored electric field management in different device regions to expand operable voltage range.
2Reliability
If multi-field plates with different heights and positions are implemented, then the operable voltage range is expanded and performance is improved, but the device structure becomes more complex
Solution Approach 1:
The field plates are arranged in a nested configuration where the first, second, and third field plates are positioned at different heights and lateral positions, with each field plate nested within the vertical or lateral space of the others. This nesting approach maximizes the electric field control capability while minimizing the additional structural footprint.
Solution Approach 2:
The field plates extend in multiple dimensions - vertically (different heights from substrate), laterally (different positions along the drift region), and in depth (different distances from the drift region). This multi-dimensional arrangement enables comprehensive electric field control throughout the device volume, improving performance without proportionally increasing surface area complexity.
3Object-affected harmful factors
If field plates are arranged in parallel and not directly connected, then electric field gradients are reduced and hot carrier injection effects are minimized, but the manufacturing process becomes more difficult
Solution Approach 1:
The drift region serves as an intermediary medium between the field plates, allowing the field plates to be electrically isolated yet functionally connected through the semiconductor material. This intermediary approach enables independent control of each field plate while maintaining overall device functionality, reducing hot carrier effects without requiring direct electrical connections between field plates.
Solution Approach 2:
Each field plate is independently doped and positioned to create locally optimized electric field distribution. The first field plate has different doping concentration and position than the second and third field plates, allowing tailored electric field control in different regions to minimize hot carrier injection effects throughout the drift region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves low conduction resistance, low figure of merit, and high breakdown voltage, enhancing device performance by reducing electric field gradients and hot carrier injection effects.
Implementation Method 1
the plurality of field plates are arranged in parallel with the gate along a width direction... whereby the drift region provides a drift current channel for the high-voltage device having multi-field plates during the conduction operation
Data Source
AI summary
A high voltage device having multi-field plates, includes: a semiconductor layer; a well; a body region; a source and a drain; a gate; a resist protection oxide region, formed on a top surface of the semiconductor layer, in connection with the top surface, and located above a drift region and in connection with the drift region; and plural field plates formed above the resist protection oxide region, wherein the plural field plates are arranged in parallel with the gate along a width direction and the plural field plates are not directly connected with one another and are arranged in parallel with one another, wherein the field plates are located above the resist protection oxide region in a vertical direction.