Multi-Filament RRAM Cell Structure for Wider Read Current Windows

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Solution Overview

Problem

Resistive random access memory (RRAM) cells with single conductive filaments suffer from performance degradation due to limited resistance, resulting in small read current differences between data states, making accurate data reading difficult.

Innovation Solution

The use of multiple RRAM elements, each forming separate conductive filaments, allows for increased read currents and improved read current windows by electrically coupling them to generate a collective data state.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple RRAM elements are used to form separate conductive filaments, then read current window is improved, but device complexity increases

Engineering Contradiction:
Improveread current windowVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The RRAM cell is divided into multiple RRAM elements (first RRAM element and second RRAM element), each forming an independent conductive filament. This segmentation allows each element to contribute separately to the read current, thereby increasing the overall read current window while maintaining functional independence of each segment

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple RRAM elements are electrically coupled together through shared electrodes (first conjunct electrode connected to second conjunct electrode, first disjunct electrode connected to second disjunct electrode). This merging combines the read currents from individual filaments to achieve a larger collective read current window, resolving the contradiction between complexity and performance

Inventive Principle:
Principle #5Merging (Combining)

2Device complexity

If single conductive filament is used, then device complexity is reduced, but read current difference between data states is limited

Engineering Contradiction:
Improvedevice complexityVSAvoidread current difference
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

Instead of using a single conductive filament, the invention segments the memory cell into multiple RRAM elements, each with its own conductive filament. This segmentation multiplies the read current contribution, thereby increasing the read current difference between data states without requiring excessive complexity in each individual element

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the parameter of read current magnitude by combining multiple parallel conductive paths. By configuring multiple RRAM elements in parallel with shared electrodes, the total read current is increased, improving the distinguishability between data states while maintaining reasonable device complexity

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the read current window and mitigates performance degradation, enabling more accurate data reading and storage in RRAM cells.

Implementation Method 1

a first RRAM element that is arranged within a dielectric structure over a substrate and that has a first conjunct electrode separated from a first disjunct electrode by a first data storage layer. A second RRAM element is arranged within the dielectric structure and has a second conjunct electrode separated from a second disjunct electrode by a second data storage layer

Methodology Applied
Scientific EffectConductive filament formation: Conduction (electrical)

Data Source

PatentUS12075634B2RRAM memory cell with multiple filaments
Publication Date: 2024.08.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12075634B2 patent drawing
  • US12075634B2 patent drawing
  • US12075634B2 patent drawing

AI summary

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element and a second RRAM element over a substrate. A conductive element is arranged below the first RRAM element and the second RRAM element. The conductive element electrically couples the first RRAM element to the second RRAM element. An upper insulating layer continuously extends over the first RRAM element and the second RRAM element. An upper inter-level dielectric (ILD) structure laterally surrounds the first RRAM element and the second RRAM element. The upper insulating layer separates the first RRAM element and the second RRAM element from the upper ILD structure.