Multi-fin FET Structure Preventing Floating Body Effect

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Solution Overview

Problem

Conventional semiconductor devices with vertical gate structures suffer from the floating body effect, which affects threshold voltage and current, and the epitaxial process is time-consuming, difficult to clean, and hard to control, leading to facet effects and reliability issues.

Innovation Solution

A multi-fin field effect transistor is designed with a substrate, oxide layer, conductive layer, and doped regions, where fin-type silicon layers are formed in trenches, eliminating the need for epitaxial processing and reducing charge accumulation, thereby enhancing device reliability and stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If a vertical gate structure is adopted to shrink device size, then device integration density is improved, but floating body effect occurs causing threshold voltage shift and current instability

Engineering Contradiction:
Improvedevice sizeVSAvoidthreshold voltage stability
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The invention divides the channel into multiple independent fins instead of using a single planar channel. Each fin acts as an independent current path with its own gate control, preventing charge accumulation that causes floating body effect while maintaining compact device footprint

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from a two-dimensional planar channel to a three-dimensional multi-fin structure. By stacking multiple fins vertically, the device achieves higher integration density while each fin maintains independent gate control to prevent floating body effects

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If epitaxial process is used to form semiconductor layers, then layer quality is improved, but process time increases and surface cleaning becomes difficult

Engineering Contradiction:
Improvelayer qualityVSAvoidprocess time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The invention extracts the problematic epitaxial growth step from the manufacturing process. Instead of forming layers through time-consuming epitaxial growth, the method uses direct deposition or other faster techniques that achieve sufficient layer quality without the drawbacks of traditional epitaxy

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention uses simpler, faster deposition techniques that may produce layers with sufficient quality for the application, accepting that the layers are not as perfectly crystalline as epitaxial layers but are formed much more quickly and easily cleaned

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Manufacturing precision

If epitaxial process is used to form semiconductor layers, then layer formation is achieved, but facet effect occurs influencing subsequent processes

Engineering Contradiction:
Improvelayer formation controlVSAvoidsubsequent process control
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The invention removes the epitaxial growth step that causes facet effects. By using alternative layer formation methods, the process avoids the directional crystal growth that creates facets, thereby simplifying subsequent processing steps

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention uses deposition methods that can replicate the desired layer structure without the complex crystallographic orientation control required in epitaxial growth, avoiding facet formation while maintaining adequate layer quality

Inventive Principle:
Principle #26Copying

Data Source

PatentUS7510955B2Method of fabricating multi-fin field effect transistor
Publication Date: 2009.03.31 PROMOS TECH INC
  • US7510955B2 patent drawing
  • US7510955B2 patent drawing
  • US7510955B2 patent drawing

AI summary

A multi-fin field effect transistor includes a substrate, an oxide layer, a conductive layer, a gate oxide layer, and a doped region is provided. The substrate is surrounded by a trench, and there are at least two fin-type silicon layers formed in the substrate in a region prepared to form a gate thereon. The oxide layer is disposed in the trench and the top surface of the oxide layer is lower than that of the fin-type silicon layers. The conductive layer is disposed in the region prepared to form a gate. The top surface of the conductive layer is higher than that of the fin-type silicon layers. The gate oxide layer is disposed between the conductive layer and the fin-type silicon layers and disposed between the conductive layer and the substrate. The doped region is disposed in the substrate on both sides of the conductive layer.