Multi-Fin MOS Structure for Low Ron and Breakdown Control
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Solution Overview
Problem
Existing high-voltage MOS transistors face challenges in reducing on-resistance (Ron) while maintaining breakdown voltage (BVD), which is crucial for improving power efficiency, especially in portable ICs.
Innovation Solution
A semiconductor structure with a substrate featuring fins, overlapping wells, epitaxial source and drain regions, a gate, trench isolation regions, and slot contacts, which are designed to reduce Ron by controlling the electric field and carrier distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional high-voltage MOS transistor structures are used, then breakdown voltage is maintained, but on-resistance remains high
Solution Approach 1:
The transistor channel is segmented into multiple fins extending in the first direction, with the gate wrapping around each fin. This segmentation increases the effective channel width and improves carrier transport, reducing on-resistance while maintaining breakdown voltage through the fin structure's inherent voltage handling capability.
Solution Approach 2:
The invention transitions from a planar channel structure to a three-dimensional fin structure with gates wrapping around multiple fins. This dimensional change increases the channel width without proportionally increasing the device footprint, improving the on-resistance to breakdown voltage ratio by enhancing carrier flow paths while maintaining voltage blocking capability.
2Productivity
If device miniaturization is pursued, then integration density improves, but on-resistance increases
Solution Approach 1:
By stacking multiple fins vertically and having the gate wrap around each fin, the invention achieves higher effective channel width in a smaller footprint. This dimensional approach allows miniaturization of the device footprint while maintaining low on-resistance through increased carrier transport pathways provided by the multi-fin structure.
Solution Approach 2:
The gate structure is nested around multiple fins in a compact arrangement, with each fin contributing to the channel width. This nested configuration maximizes the channel width within a minimized footprint, achieving high integration density without sacrificing on-resistance performance.
3Stability of the object's composition
If conventional trench isolation is used, then device isolation is achieved, but electric field management is insufficient
Solution Approach 1:
The trench isolation regions are strategically positioned and dimensioned to provide localized electric field management at critical interfaces. The isolation trenches are configured with specific depths and widths to control charge distribution and electric field contours in the drift region, improving breakdown voltage and electric field management while maintaining device isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure effectively reduces on-resistance (Ron) and enhances operating performance by optimizing carrier distribution and electric field management.
Implementation Method 1
an epitaxial source region having the second conductive type disposed on the plurality of fins within the first well; an epitaxial drain region having the second conductive type disposed on the plurality of fins within the second well
Implementation Method 2
a gate disposed on the plurality of fins between the epitaxial source region and the epitaxial drain region, wherein the gate extends along a second direction
Implementation Method 3
a trench isolation region disposed within the second well between the gate and the epitaxial drain region
Data Source
AI summary
A semiconductor structure includes a substrate with a plurality of fins, a first well, and a second well in the substrate. The plurality of fins partially overlaps the first well and partially overlaps the second well. An epitaxial source region is arranged on the plurality of fins in the first well, and an epitaxial drain region is arranged on the plurality of fins in the second well. A gate is arranged on the plurality of fins between the epitaxial source region and the epitaxial drain region. A trench isolation region is disposed in the second well between the gate and the epitaxial drain region. A slot contact is disposed on the trench isolation region.