Multi-Fin Transistor Layout for Mixed Power and Logic on One Die
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Solution Overview
Problem
Integrated circuit design, particularly for system-on-chip (SOC) devices, faces challenges in achieving both low-power dissipation and high performance with a single transistor type, as existing finned transistor configurations are limited to a single fin height/width dimension, making it difficult to meet divergent requirements for logic and power management areas.
Innovation Solution
The technique involves lithographically defining areas to be trimmed using a trim etch process, which can narrow the width and height of fin channel regions, allowing for multiple fin dimensions on a single die, enabling varied transistor geometries suitable for different applications by selectively trimming channel regions during a replacement gate process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single fin height/width dimension is used for all transistors on a die, then manufacturing is simplified, but it becomes impossible to achieve both low-power dissipation and high performance devices on the same die
Solution Approach 1:
The patent applies local quality by creating different fin dimensions in different regions of the semiconductor die. Specifically, first fins are formed with a first height in a first region, while second fins are formed with a second height in a second region. This allows transistors in different areas of the die to have different performance characteristics - enabling both low-power dissipation devices and high performance devices to coexist on the same die without requiring a single uniform fin dimension across the entire chip.
2Adaptability or versatility
If multiple fin dimensions are created on a single die, then both low-power and high-performance transistors can be achieved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor die into multiple regions with different fin dimensions. The method segments the fin formation process into distinct stages: forming a patterned layer with first pitch, performing a first trim etch to create first fins with first height, then forming a second patterned layer with second pitch, and performing a second trim etch to create second fins with second height. This segmented approach allows multiple fin dimensions to be achieved through a systematic, multi-step fabrication process rather than requiring entirely different manufacturing methods.
Solution Approach 2:
The patent applies preliminary action by performing the first trim etch to create fins of the first height before forming the second patterned layer and performing the second trim etch. This sequential approach where earlier steps prepare the structure for subsequent steps enables the creation of multiple fin dimensions in an organized manner, where the first set of fins is established and then the second set is created in different regions, rather than attempting to create all variations simultaneously.
3Adaptability or versatility
If trim etch processes are used to narrow fin dimensions, then multiple fin channel dimensions can be achieved on a single die, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies the intermediary principle by using patterned layers as mediating structures between the lithography process and the final fin dimensions. The first patterned layer with first pitch and the second patterned layer with second pitch serve as intermediaries that define the regions where different fin heights will be created. These patterned layers act as masks during the trim etch processes, allowing precise control over which fins are trimmed to what height, thereby managing the manufacturing precision requirements through well-defined intermediate structures rather than direct patterning of the fins themselves.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of integrated circuits with diverse transistor performance sections, optimizing battery life and power management by allowing multiple fin dimensions and channel heights on a single die, enhancing the functionality of SOC devices.
Implementation Method 1
lithographically defining areas to be trimmed using a trim etch process, which can narrow the width and height of fin channel regions
Data Source
AI summary
Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications.