Multi-Finger Inverter Layout for Higher Output Current
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Solution Overview
Problem
Existing semiconductor integrated circuit devices face challenges in achieving a small occupying area and effective output current characteristics in inverter chain structures used for delay circuits and oscillators.
Innovation Solution
The proposed solution involves an inverter design that includes at least one PMOS transistor and one NMOS transistor, where the sources have a single finger region and the drains have a multi-finger region, arranged parallel to each other. This configuration improves the output current characteristic and reduces voltage loss due to high contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inverter design is used, then occupying area is reduced, but output current characteristic deteriorates and voltage loss increases
Solution Approach 1:
The drain region is segmented into multiple finger regions arranged in parallel, while the source region remains as a single unified region. This segmentation increases the number of current paths from the drain to source, improving output current characteristic and reducing contact resistance without proportionally increasing the occupying area, as the fingers are arranged compactly in parallel
Solution Approach 2:
The drain finger regions are extended in a direction substantially perpendicular to the source region extension direction, utilizing two-dimensional space efficiently. This dimensional arrangement allows multiple current paths to be packed into a compact area, improving current characteristic while minimizing area increase
2Reliability
If multi-finger drain region is implemented, then output current characteristic is improved, but device complexity increases
Solution Approach 1:
Multiple drain finger regions are merged into a single transistor structure that shares a common source region and gate. This combining approach improves output current characteristic through multiple current paths while avoiding the full complexity of multiple separate transistors, as the shared components reduce overall structural complexity
Solution Approach 2:
The multi-finger configuration is applied specifically to the drain region where current extraction is critical, while the source region maintains a simple single-finger structure. This localized application of complexity optimizes output current characteristic without unnecessarily complicating the entire transistor structure
Data Source
AI summary
An inverter including at least one PMOS transistor and at least one NMOS transistor. The PMOS transistor including a first gate, a first source and a first drain. The first gate may be connected to an input signal line. The first source may be connected to a power voltage line. The first drain may be connected to an output signal line. The NMOS transistor including a second gate, a second source and a second drain. The second gate may be connected to the input signal line. The second source may be connected to a ground voltage line. The second drain may be connected to the output signal line.