Multi-Finger Gilbert Mixer Layout for Symmetric LO Paths
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Solution Overview
Problem
Gilbert mixers suffer from frequency-dependent local oscillator (LO) leakage due to asymmetry in the circuit layout, which degrades radar sensitivity in Doppler Division Multiplexing (DDM) radar systems and limits error vector magnitude (EVM) and channel throughput in communication systems.
Innovation Solution
A symmetrical Gilbert mixer layout is achieved by aligning multi-finger field effect transistor (FET) devices orthogonally, merging devices to equalize trace lengths, and using symmetrical gate and current interconnects to minimize LO leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional Gilbert mixer layout is used, then the circuit is simple to manufacture, but LO leakage occurs due to asymmetry in trace lengths
Solution Approach 1:
The patent intentionally introduces asymmetry in the form of dummy trace elements to compensate for inherent layout asymmetries. By adding compensating trace length to shorter paths, the overall signal path lengths become equalized, resolving the LO leakage problem caused by unequal traces while maintaining a manageable layout structure.
Solution Approach 2:
The patent addresses trace length equality by operating in the dimensional space of trace routing, adding dummy traces in strategic locations to extend shorter paths. This dimensional approach to trace length compensation allows equalization of signal paths without fundamentally redesigning the entire mixer architecture.
2Reliability
If trace lengths are equalized to reduce LO leakage, then radar sensitivity improves, but the circuit layout becomes more complex
Solution Approach 1:
The patent uses dummy trace elements as disposable, non-functional routing elements that serve solely to equalize trace lengths. These dummy traces are simple geometric additions that do not perform active circuit functions but effectively compensate for path length differences, improving radar sensitivity without requiring complex active circuit modifications.
3Adaptability or versatility
If multi-finger FET devices are used, then device integration is improved, but asymmetry in gate finger connections causes LO leakage
Solution Approach 1:
The patent compensates for the inherent asymmetry in multi-finger FET gate connections by introducing dummy trace elements. The dummy traces are strategically placed to equalize the total path length from each gate finger to its corresponding voltage rail, ensuring symmetric signal paths despite the asymmetric physical arrangement of multiple gate fingers.
Solution Approach 2:
The patent segments the gate connection paths into multiple discrete trace segments, allowing independent adjustment of each segment's length. By dividing the connection paths and adding dummy segments to shorter paths, the overall symmetry is achieved while maintaining the integrated multi-finger FET structure.
Data Source
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AI summary
The disclosure relates to a Gilbert mixer for a radar transceiver. Example embodiments include a Gilbert mixer (1800) comprising: first and second multi-finger field effect transistor, FET, devices (1101, 1101'), each FET device (1101, 1101') comprising a plurality of gate fingers (G1-G12, G1 '-G12') arranged along a longitudinal axis (L, L') between alternating source terminals (S1-S6) and drain terminals (D1-D7), wherein the plurality of gate fingers (G1-G4, G1'-G4') of each FET device (1101, 1101') extend transverse to the longitudinal axis (L, L') of the FET devices (1101, 1101'); first and second pairs of voltage rails (103a,b, 103a',b') arranged parallel to the longitudinal axis (L, L') across the first and second FET devices (1101, 1101') respectively, each of the first and second pairs of voltage rails (103a,b, 103a',b') comprising an upper rail (103a, 103a') and a lower rail (103b, 103b'); a first gate interconnect (111) connecting the upper rail (103a) of the first pair of voltage rails (103a,b) and the lower rail (103b') of the second pair of voltage rails (103a',b') to a first input terminal (vg0); and a second gate interconnect (112) connecting the lower rail (103b) of the first pair of voltage rails (103a,b) and the upper rail (103a') of the second pair of voltage rails (103a',b') to a second input terminal (vg180),wherein alternating adjacent pairs of gate fingers (G1-G12) of the first FET device (1101) are connected to respective upper and lower rails (103a, 103b) of the first pair of voltage rails (103a,b) and alternating adjacent pairs of gate fingers (G1'-G12') of the second FET device (1101') are connected to respective upper and lower rails (103a', 103b') of the second pair of voltage rails (103a',b').