Multi-Fingered Diode Layout for Low-Capacitance ESD Protection
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Solution Overview
Problem
Diodes used in ESD protection circuits face challenges in responding quickly to ESD events due to high parasitic capacitance, which can lead to inadequate protection of semiconductor chips from voltage surges.
Innovation Solution
The design of a diode with reduced parasitic capacitance is achieved by minimizing overlapping metal layers, reducing fringe capacitance through strategic placement and segmentation of metal electrodes, and ensuring that all metal levels are at the same voltage potential to prevent capacitance between them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the diode size is increased to dissipate larger current, then the current dissipation capability is improved, but the parasitic capacitance increases which slows down the response time
Solution Approach 1:
The diode structure is divided into multiple fingers with separate anode and cathode regions. Each finger acts as an independent current path, allowing the total current dissipation capability to be increased by adding more fingers without proportionally increasing the parasitic capacitance, since the capacitance is distributed across multiple smaller regions rather than one large region.
Solution Approach 2:
The patent utilizes multiple metal layers stacked vertically to create current paths in the vertical dimension. By routing current through multiple layers and using vias to connect them, the design achieves high current dissipation capability without increasing the horizontal footprint area, thereby limiting the increase in parasitic capacitance.
2Power
If overlapping metal layers are added to increase current dissipation capability, then the power handling is improved, but the overlapping parasitic capacitance increases
Solution Approach 1:
Metal layers that are placed in overlapping positions are connected to the same electrical potential (either both anode or both cathode). By ensuring that overlapping metal layers are at equipotential, the patent eliminates parasitic capacitance between them, as no voltage difference exists to drive capacitive coupling. This allows multiple metal layers to be used for current dissipation without introducing harmful overlapping capacitance.
3Area of stationary object
If metal layers are positioned closer together to reduce area, then the device area is reduced, but the fringe capacitance between adjacent layers increases
Solution Approach 1:
The patent extracts or removes metal layers from positions where they would be adjacent to opposite-polarity metal layers. Specifically, metal layers are positioned only over regions of the same polarity (anode over anode, cathode over cathode), and are deliberately placed away from adjacent metal layers of opposite polarity. This extraction of problematic adjacent positioning eliminates fringe capacitance while maintaining compact device area through efficient use of vertical stacking.
Data Source
AI summary
A diode and method of design the layout of the same having reduced parasitic capacitance is disclosed. In particular, the diode for providing fast response protection of an RF circuit from a high power noise event, such as an ESD, voltage spike, power surge or other noise is disclose. The parasitic capacitance in disclosed circuit is a greatly reduced compared to the prior art, thus significantly increasing the speed of the response to dissipate all high power noise events.