Multi-format Multiplier Unit for Wireless Signal Processing
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Solution Overview
Problem
Advanced wireless networks require efficient hardware acceleration for operations like beamforming and path searching, but existing solutions are inflexible and costly due to the need for dedicated ASICs or on-chip coprocessors, and multiplication operations are resource-intensive.
Innovation Solution
A multi-format multiplier unit that combines two multiplication functions within the same hardware, using a first multiplier for unequally weighted partial products, a second multiplier for equally weighted partial products, a multiplexer to select between them, and a carry save adder array to combine the results, allowing for shared hardware resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dedicated ASIC or on-chip coprocessor units are implemented for wireless processing algorithms, then processing performance is improved, but chip area and power consumption increase significantly
Solution Approach 1:
The multiplier unit is designed to perform multiple multiplication functions (complex multiplication, real multiplication, and unweighted multiplication) using the same hardware resources. The carry-save adder array and multiplexers are shared across different multiplication modes, allowing one hardware unit to replace what would traditionally require multiple dedicated units, thereby reducing chip area while maintaining processing performance for various wireless algorithms
2Area of stationary object
If hardware sharing is implemented to reduce chip area, then area efficiency is improved, but design complexity increases
Solution Approach 1:
The multiplier unit is segmented into distinct functional components: a first multiplier for generating unequally weighted partial products, a second multiplier for equally weighted partial products, multiplexers for selection, and a carry-save adder array. This segmentation allows each component to be optimized for its specific function while being shared across multiple multiplication modes, managing design complexity through modular organization
Solution Approach 2:
The multiplier unit incorporates dynamic switching capability through multiplexers that can select between different multiplication modes (complex, real, unweighted) based on operational requirements. This dynamic reconfiguration allows the same hardware to adapt to different algorithmic needs without requiring separate dedicated circuits for each mode, balancing area efficiency with operational flexibility
3Adaptability or versatility
If complex algorithms like path search and matrix multiplication are implemented, then processing capability is improved, but resource consumption increases
Solution Approach 1:
The multiplier unit supports multiple multiplication types (complex, real, unweighted) required by different wireless algorithms such as path search and matrix multiplication using shared hardware resources. By eliminating the need for separate dedicated multipliers for each algorithm type, the design reduces overall power consumption while maintaining the capability to execute complex wireless processing algorithms
Data Source
AI summary
Multiplication engines and multiplication methods are provided. A multiplication engine for a digital processor includes a first multiplier to generate unequally weighted partial products from input operands in a first multiplier mode; a second multiplier to generate equally weighted partial products from input operands in a second multiplier mode; a multiplexer to select the unequally weighted partial products in the first multiplier mode and to select the equally weighted partial products in the second multiplier mode; and a carry save adder array configured to combine the selected partial products in the first multiplier mode and in the second multiplier mode.