Multi-FPGA Clock Packet Synchronization for Large Logic Designs
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Solution Overview
Problem
The capacity of Field Programmable Gate Arrays (FPGAs) to implement large-scale chip designs is limited, and existing methods for connecting multiple FPGAs face challenges in ensuring synchronized data communication, leading to bottlenecks and difficulties in maintaining the same functionality across multiple FPGAs.
Innovation Solution
A system comprising a main FPGA and sub-FPGAs, where the main FPGA detects the positive edge of a user clock, generates a clock packet, and provides it to sub-FPGAs, enabling synchronized clock usage through a gated user clock, allowing for efficient data processing and communication across FPGAs without requiring synchronized clocks or the same clock domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple FPGAs are connected using general-purpose input/output (GPIO) line-by-line connection method, then data communication between FPGAs can be established, but it is difficult to implement a large number of lines and bottlenecks occur in data communication
Solution Approach 1:
The patent segments the data communication interface into multiple lanes (e.g., 16 lanes) where each lane can independently transmit data. This segmentation allows parallel data transmission across multiple FPGAs, significantly increasing the number of effective communication lines and eliminating bottlenecks associated with GPIO connections.
Solution Approach 2:
The patent transitions from one-dimensional sequential GPIO connections to multi-dimensional parallel communication by organizing data transmission across multiple simultaneous lanes. This dimensional change enables massive throughput by allowing multiple data bits to be transmitted concurrently across different FPGA devices.
2Reliability
If FPGAs are connected using Chip to Chip (C2C) or Die to Die (D2D) method, then connection capability is improved, but handshaking process requires signals to be sent and received within the same clock, requiring additional logic and design
Solution Approach 1:
The patent introduces an intermediary mechanism where data is packaged into protocol-defined structures with explicit timing and synchronization information. This intermediary packaging layer allows FPGAs to communicate without requiring complex handshaking logic, as the protocol itself manages timing and clock domain crossing transparently.
Solution Approach 2:
The patent changes the communication parameters by defining specific protocol rules for data packaging, timing, and transmission. By establishing fixed parameters for data width, timing relationships, and clock synchronization methods, the system eliminates the need for dynamic handshaking logic while maintaining reliable synchronized communication.
3Adaptability or versatility
If the chip design or logic scale exceeds a certain size, then functionality requirements increase, but it is not possible to implement all chip designs or logics in one FPGA
Solution Approach 1:
The patent segments large-scale chip designs into multiple FPGAs that can be distributed across different devices. Each FPGA implements a portion of the overall logic, and the high-speed parallel interconnect fabric enables these segmented implementations to function as a unified system, thereby achieving designs that exceed the capacity of any single FPGA.
Solution Approach 2:
The patent creates a universal interconnect fabric that can accommodate various FPGA configurations and scaling scenarios. The same high-speed parallel communication infrastructure supports different numbers of FPGAs, different data widths, and various timing requirements, providing a multi-functional platform for implementing chip designs of varying scales.
Data Source
AI summary
A Field Programmable Gate Array (FPGA) system includes a main FPGA and one or more sub-FPGAs connected to the main FPGA. The main FPGA is configured to detect a positive edge of a pulse included in a user clock using a sampling clock of the main FPGA, generate a flag using the detected positive edge, generate a clock packet indicating the generated flag, and provide the generated clock packet to any one of the one or more sub-FPGAs.