Multi-FPGA Graph Processing Optimization via Locality Partitioning

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Solution Overview

Problem

Existing multi-FPGA graph processing systems face challenges with high communication overhead and low computation-to-communication ratio due to inefficient load balancing and task assignment, leading to limited scalability and performance.

Innovation Solution

A graph processing optimization method that considers the locality of graphs during partitioning to minimize communication overhead, using dynamic task assignment and a memory nested dissection scheme to achieve load balance between FPGA accelerators, thereby improving processing efficiency and reducing unnecessary communication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional load balancing methods are used in multi-FPGA graph processing systems, then load distribution between FPGAs is improved, but communication overhead increases significantly

Engineering Contradiction:

Improveload distributionVSAvoidcommunication overhead

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The patent segments the graph data into multiple sub-graphs and assigns them to different FPGA accelerators for parallel processing. Each FPGA processes its assigned sub-graph independently, reducing the need for inter-FPGA communication while maintaining load distribution. This segmentation approach allows the system to achieve both load balancing and reduced communication overhead by dividing the processing workload at the data level.

Inventive Principle:

Principle #1Segmentation

2Productivity

If graph data is partitioned to achieve load balance between FPGAs, then processing efficiency is improved, but communication overhead increases due to data transmission

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidcommunication time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent performs preliminary partitioning of the graph data into sub-graphs based on locality principles before distribution to FPGAs. By pre-processing the data to identify and group related vertices and edges together, the system minimizes the need for inter-FPGA communication during the actual processing phase. This preliminary organization of data ensures that each FPGA receives a self-contained sub-graph that can be processed with minimal external communication.

Inventive Principle:

Principle #10Preliminary action

3Power

If multi-FPGA system is used to process large-scale graphs, then processing capacity is improved, but computation-to-communication ratio decreases

Engineering Contradiction:

Improveprocessing capacityVSAvoidcomputation-to-communication ratio

Core Design Contradiction:

PowerVSProductivity

Solution Approach 1:

The patent applies local quality by organizing graph data according to locality principles, where vertices and edges that are frequently accessed together are grouped within the same sub-graph assigned to a single FPGA. This local organization ensures that each FPGA processes data with high locality, maximizing the utilization of its computing resources while minimizing the need for communication with other FPGAs. The system thus achieves high processing capacity while maintaining a favorable computation-to-communication ratio through localized data processing.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS11288221B2Graph processing optimization method based on multi-FPGA accelerator interconnection

Publication Date: 2022.03.29 HUAZHONG UNIV OF SCI & TECH

AI summary

A graph processing optimization method that addresses the problems such as the low computation-to-communication ratio in graph environments, and high communication overhead as well as load imbalance in heterogeneous environments for graph processing. The method reduces communication overhead between accelerators by optimizing graph partitioning so as to improve system scalability.