Multi-FPGA Packet Routing for Scalable Communication Management
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Solution Overview
Problem
Current solutions for data transmission and communication between multiple field programmable gate array (FPGA) devices are not scalable and become difficult to manage as the number of FPGAs increases, lacking efficient protocols for managing complex systems.
Innovation Solution
A communication system and method that utilize routing information in packets to enable transmission between multiple FPGAs, with different transmission formats for non-post, post, and memory writing modes, allowing packets to be sent to any FPGA device, and incorporating bus, device, and function sequence numbers for precise routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple FPGAs are used to share computational load, then computing power and resource configuration requirements are met, but data transmission and communication management becomes difficult
Solution Approach 1:
The communication protocol segments packet routing into distinct components: routing information field for destination identification, bus sequence number for arbitration, device sequence number for port selection, and function sequence number for module routing. This segmentation allows each component to handle specific routing tasks independently, making the overall system manageable even as FPGA count increases
Solution Approach 2:
The communication protocol is designed to be universal across multiple FPGAs, with the same packet format and routing mechanism working consistently regardless of which FPGA is the source or destination. The routing information structure serves multiple functions: identifying destination, determining routing path, and selecting specific ports and modules, eliminating the need for separate addressing mechanisms
2Adaptability or versatility
If existing transmission protocols between two FPGAs are used, then basic communication is achieved, but scalability is insufficient when number of FPGAs increases
Solution Approach 1:
The protocol adds multiple dimensional fields to the packet structure: routing information field, bus sequence number, device sequence number, and function sequence number. This multi-dimensional addressing space enables identification and routing to any combination of FPGAs, ports, and modules, providing scalability without complicating the routing logic
Solution Approach 2:
The routing information acts as an intermediary structure that mediates between the sender and receiver FPGAs. It contains all necessary routing decisions in a standardized format, allowing intermediate FPGAs to forward packets correctly without needing to know the complete communication topology or manage complex routing logic
3Adaptability or versatility
If routing information is added to packets, then packets can be transmitted to any FPGA device, but packet format complexity increases
Solution Approach 1:
The routing information is segmented into distinct fields with specific purposes: routing information field for destination identification, bus sequence number for arbitration, device sequence number for port selection, and function sequence number for module routing. This segmentation makes the complex routing functionality manageable and implementable
Solution Approach 2:
The protocol uses sequence numbers (bus sequence number, device sequence number, function sequence number) as parameter changes to enable flexible routing. These numeric parameters provide a simple way to differentiate between multiple FPGAs, ports, and modules without requiring complex identifier formats
Data Source
AI summary
Provided is a communication system and a communication method. The communication system includes multiple field programmable gate array (FPGA) devices. Each of the FPGA devices is electrically connected to another one of the FPGA devices. A first FPGA device is configured to determine a format of a packet. When the format of the packet belongs to a first transmission format or a second transmission format, the first FPGA device adds a routing information to the packet and transmits the packet to a second FPGA device.