Multi-FPGA PCIe Routing for Low-Latency Multi-Legged Orders
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional software-based systems for multi-legged order transactions suffer from high latency due to separate net processing and order matching layers connected through 10G Ethernet, leading to reduced throughput and rejection of orders involving tokens processed on different machines.
Innovation Solution
A multiple Field Programmable Gate Array (FPGA) system with a multi-port PCIe switch connects FPGAs for low-latency communication, enabling each FPGA to process tokens locally or route them to appropriate boards via PCIe ports, facilitating efficient multi-legged order processing across multiple FPGAs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional software-based systems with separate net processing and order matching layers connected through 10G Ethernet are used, then system reliability is maintained, but latency is high (order of 10 microseconds) and throughput is reduced
Solution Approach 1:
The patent combines the net processing layer and order matching layer into a single integrated system implemented on FPGAs, eliminating the need for separate machines and Ethernet communication. This merging of previously separate layers directly reduces latency while maintaining system reliability.
Solution Approach 2:
The patent introduces PCIe switches as an intermediary communication mechanism between FPGAs, replacing the Ethernet network infrastructure. This intermediary provides low-latency communication paths while maintaining the distributed architecture needed for processing multi-legged orders across multiple tokens.
2Adaptability or versatility
If multiple FPGAs are used for processing tokens on different machines, then adaptability for multi-legged orders is improved, but communication latency increases
Solution Approach 1:
The PCIe switch acts as an intermediary that enables fast communication between multiple FPGAs processing different tokens. This allows the system to maintain adaptability for multi-legged orders across multiple FPGAs while minimizing communication latency through direct PCIe connections rather than Ethernet.
Solution Approach 2:
The system segments the processing of different tokens across multiple FPGAs, with each FPGA handling specific tokens. The PCIe switch coordinates this segmentation, allowing parallel processing while maintaining low-latency communication for multi-legged order execution.
3Productivity
If Ethernet communication is used between matching engines, then system simplicity is maintained, but throughput is limited and cannot handle huge volume of orders
Solution Approach 1:
The PCIe switch serves as a high-speed intermediary communication infrastructure that replaces Ethernet, enabling throughput capable of handling huge volumes of orders per second while maintaining manageable system complexity through standardized PCIe interfaces.
Solution Approach 2:
The patent replaces the mechanical/Ethernet-based communication system with an electronic PCIe-based system. This substitution enables significantly higher throughput by utilizing the faster electrical communication paths of PCIe compared to Ethernet, while keeping the overall system architecture relatively simple.
Data Source
AI summary
Conventionally, for processing multi-legged orders, matching engines were implemented in software and were connected through Ethernet which is very slow in terms of throughput. Such traditional trading systems failed to process orders of tokens on different machines and these were summarily rejected. Present disclosure provides multiple FPGA system being optimized for processing/executing multi-legged orders. The system includes a plurality of FPGAs which are interconnected for communication via a PCIe port of a multi-port PCIe switch. Each FPGA comprise a net processing layer, a matcher, and a look-up table. Each FPGA is configured to process tokens (e.g., securities, etc.). If orders to be processed are for tokens on same FPGA where the order is received, then tokens are processed locally. Else net processing layer of a specific FPGA routes to specific order request to another FPGA where the tokens (securities) are located thereby reducing the latency and improving overall throughput.