Multi-FPGA Clock Generation With Phase-Aligned Local Clocks
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Solution Overview
Problem
Current FPGA-based prototyping systems face limitations in bandwidth due to a limited number of interconnects, leading to clock signal misalignment and performance degradation, especially as the number of FPGAs increases, and the existing methods to address these issues are inadequate.
Innovation Solution
The method involves replicating clock generators on each FPGA using a reference clock and phase-locked loop circuitry to generate aligned edge clock signals, ensuring synchronized clock edges across all FPGAs, thereby eliminating the need for clock signal transmission between FPGAs and freeing up bandwidth for other signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are distributed over interconnects between FPGAs, then clock signals can be transmitted to multiple FPGAs, but system bandwidth is severely reduced and clock edges become misaligned
Solution Approach 1:
The system divides the clock generation function into separate segments, with each FPGA containing its own local clock generator. This eliminates the need to distribute clock signals through interconnects, as each FPGA generates its own clocks independently from a reference clock received through dedicated low-skew paths.
Solution Approach 2:
A reference clock signal acts as an intermediary that is distributed to all FPGAs through dedicated low-skew interconnects. Each FPGA uses this reference clock as input to its local clock generator, ensuring synchronized clock edges without consuming general-purpose interconnect bandwidth.
2Reliability
If clock signals are distributed over interconnects between FPGAs, then clock signals can be transmitted to multiple FPGAs, but clock edges become misaligned causing waveform capture distortion
Solution Approach 1:
The system uses dedicated low-skew interconnects to distribute the reference clock signal to all FPGAs simultaneously, ensuring that all FPGAs receive the reference clock at nearly the same time. This creates equipotential conditions for clock distribution, eliminating skew and ensuring aligned clock edges across all FPGAs.
3Adaptability or versatility
If the number of FPGAs increases in the prototyping system, then more circuit design logic can be implemented, but system bandwidth becomes increasingly limited
Solution Approach 1:
Each FPGA is equipped with its own local clock generator, segmenting the clock generation function across all FPGAs. This eliminates the bottleneck of centralized clock distribution and allows the system to scale to any number of FPGAs without consuming general-purpose interconnect bandwidth for clock signals.
Solution Approach 2:
The local clock generators in each FPGA provide universal clock generation capability, allowing each FPGA to generate its own clocks independently. This multi-functional approach enables the system to accommodate any number of FPGAs while maintaining full interconnect bandwidth availability for data and control signals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for faster and more accurate prototyping by ensuring synchronized clock signals across multiple FPGAs, enhancing system performance and reducing clock misalignment, thus enabling the circuit design to run closer to the intended clock speed without degrading system bandwidth.
Implementation Method 1
each of the plurality of programmable logic devices includes an aligned edge clock generator that receives the reference clock and generates a local reference clock signal that drives at least one local design clock signal based on the local reference clock signal
Data Source
AI summary
An apparatus and method for fast phase aligned local generation of design clocks on a multiple FPGA system via clock generator replication is described. The apparatus includes a reference clock that generates a clock signal have a reference frequency and a plurality of programmable logic devices. Each programmable logic device includes phase locked loop circuitry that receives the clock signal from the reference clock and generates a local reference clock signal having a frequency based on the reference frequency and a clock generator that receives the local reference clock signal and generates local design clocks based on the local reference clock signal. Because each local design clock generator is synchronized by the same reference clock over a low skew line, the edges of the local design clocks are aligned.