Multi-FPGA Waveform Data Processing With Timestamped Storage

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Solution Overview

Problem

In large-scale SOC chip design simulations, the traditional method of storing waveform data in sequence by time sequence faces challenges with speed and reliability due to increased complexity and data volume, leading to potential data loss or disorder.

Innovation Solution

A method and system for processing simulation data that involves simultaneously collecting waveform data from multiple FPGAs, adding a timestamp to each data set, performing real-time data compression using the LZ77 algorithm, and storing the data in a link list structure synchronized by timestamps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If waveform data from multiple FPGAs is collected and stored in sequence according to time sequence, then the data storage method is simple, but data loss or disorder occurs due to processing delay when the number of FPGAs increases

Engineering Contradiction:

Improvesimplicity of data storage methodVSAvoidintegrity of waveform data

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the waveform data processing by introducing timestamp-based segmentation. Each FPGA's data is marked with timestamps, and data from multiple FPGAs is organized into time-synchronized segments. This allows the system to handle multiple data streams independently while maintaining overall synchronization, preventing data loss and disorder that occurs with simple sequential storage.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If the scale of SOC chip is expanded, then the simulation capability is improved, but the amount of waveform data increases rapidly causing bandwidth bottleneck

Engineering Contradiction:

Improvesimulation capabilityVSAvoiddata transmission efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent extracts redundant information from waveform data through compression processing. By identifying and removing duplicate or redundant data patterns, the system reduces the overall data volume that needs to be transmitted and stored, thereby alleviating the bandwidth bottleneck caused by increased SOC chip scale and multiple FPGAs.

Inventive Principle:

Principle #2Taking out (Extraction)

3Adaptability or versatility

If multiple FPGAs are used for large-scale SOC simulation, then the simulation scope is expanded, but the processing speed decreases due to bandwidth limitations

Engineering Contradiction:

Improvesimulation scopeVSAvoiddata processing speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent applies compression processing to waveform data before storage and transmission. By pre-compressing the data from multiple FPGAs, the system reduces the amount of data that needs to be processed subsequently, thereby maintaining processing speed even when the simulation scope is expanded to include multiple FPGAs.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12333232B2Method and system for processing simulation data

Publication Date: 2025.06.17 SHENZHEN GOUWEIXIN TECH CO LTD

AI summary

The present invention discloses a method and system for processing simulation data. The method includes: simultaneously collecting the simulation waveform data of said multiple FPGAs and adding a time stamp to the waveform data of each FPGA collected in each collection period, and storing the waveform data of the multiple FPGAs in the form of a link list according to the time stamp. The technical solution of the present invention can ensure no disorder of the waveform data of multiple FPGAs.