Multi-function Summing Machine for Parallel Image Processing
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Solution Overview
Problem
Conventional image processing systems require multiple passes through an image to calculate and sum functions over pixels, making them computationally intensive and inefficient, especially when bundling multiple driver assistance systems like automatic high-beam control, traffic sign recognition, lane departure warning, and forward collision warning on a single hardware platform.
Innovation Solution
A multifunction summing machine with an arithmetic core that includes multiple function processing units capable of parallel processing and simultaneous summation of intensity data across multiple image windows of varying sizes and overlap, allowing for efficient computation and storage of results in a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple passes through the image are performed to calculate and sum functions over pixels, then accurate function values can be obtained for each window, but computational intensity and processing time increase significantly
Solution Approach 1:
The image is divided into multiple overlapping windows, and the processing is segmented into multiple passes where each pass handles a different window. This allows parallel or sequential processing of different regions without requiring multiple complete image traversals for each function, reducing redundant computations while maintaining accuracy.
Solution Approach 2:
The patent performs preliminary calculations of function values during the first pass through the image window and stores them in local memory cells. Subsequent passes can then retrieve and accumulate these pre-calculated values without re-computing the functions, significantly reducing computational intensity while maintaining measurement precision.
2Device complexity
If multiple driver assistance systems are bundled on a single hardware platform, then cost and space are reduced, but computational intensity and processing requirements increase
Solution Approach 1:
The patent implements a universal processing architecture that can handle multiple driver assistance functions (lane departure warning, forward collision warning, traffic sign recognition, automatic high-beam control) using the same hardware platform and processing pipeline. This multi-functional design reduces overall device complexity and cost while managing computational intensity through efficient resource sharing and parallel processing capabilities.
Solution Approach 2:
Multiple function processing units are merged into a single arithmetic core that shares common resources including image memory, intensity data buffers, and accumulator structures. This consolidation reduces hardware complexity and space requirements while distributing computational load across multiple functional units operating in parallel, thereby managing overall computational intensity.
3Productivity
If multiple function processing units are used for parallel processing, then processing speed and productivity improve, but device complexity and hardware requirements increase
Solution Approach 1:
Multiple function processing units are nested within a single arithmetic core structure, with each processing unit containing its own processing core and accumulator but sharing common image memory, data buffers, and control logic. This nested architecture enables parallel processing and improved productivity while containing device complexity through hierarchical organization and resource sharing.
Solution Approach 2:
Each function processing unit within the arithmetic core is customized with specific processing capabilities and accumulator configurations tailored to its designated function (e.g., gradient calculation for LDW, intensity summation for AHC). This local optimization allows each unit to process its specific function efficiently while the overall arithmetic core maintains a unified, manageable structure through standardized interfaces and shared resources.
Data Source
AI summary
A system for processing an image including multiple pixels and intensity data thereof. An image memory is adapted for storing the image. An arithmetic core is connectible to the image memory and adapted for inputting the intensity data. The arithmetic core includes a multiple function processing units. One or more of the function processing units includes (i) a processing core adapted for computation of a function of the intensity data and for producing results of the computation, (ii) a first and (iii) a second accumulator for summing the results; and storage adapted to store the results. The function processing units are configured to compute the functions in parallel and sum the results simultaneously for each of the pixels in a single clock cycle.