Multi-Functional Transistor Gate Structures for Threshold Voltage Control
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Solution Overview
Problem
The challenge of forming semiconductor devices with different gate structures to achieve varying threshold voltages becomes increasingly complex as dimensions continue to scale down, particularly in GAA FETs, finFETs, and MOSFETs, due to the difficulty in forming distinct gate oxide layer thicknesses during the gate replacement process.
Innovation Solution
The semiconductor device incorporates non-I/O and I/O FETs with different gate structures, where the I/O FET has a thicker thermal oxide layer to achieve a higher threshold voltage, while the non-I/O FET uses a non-thermal oxide layer, allowing for simultaneous formation of gate structures with equal thicknesses during the gate replacement process, and includes lightly-doped S/D regions to minimize hot carrier effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If distinct gate oxide layer thicknesses are formed during the gate replacement process to achieve different threshold voltages, then the threshold voltage control is improved, but the device complexity and manufacturing difficulty increase significantly
Solution Approach 1:
The patent applies local quality by forming a thermal oxide layer selectively on the I/O FET gate structure while the non-I/O FET receives only a non-thermal oxide layer. This localized differentiation in oxide formation methodology allows each FET type to achieve its required threshold voltage characteristics through tailored gate oxide properties, resolving the contradiction between precise threshold control and manufacturing complexity
Solution Approach 2:
The thermal oxide layer is formed on the I/O FET gate structure before the gate replacement process begins. This preliminary action ensures that the I/O FET will have the necessary thicker oxide layer for higher threshold voltage without requiring complex modifications during the gate replacement process itself, thereby simplifying the overall manufacturing procedure
2Manufacturing precision
If the I/O FET uses a thicker gate oxide layer to achieve higher threshold voltage, then the threshold voltage is improved, but the manufacturing process complexity increases
Solution Approach 1:
The gate oxide layer formation is segmented into two distinct processes: a thermal oxide formation step for the I/O FET and a non-thermal oxide formation step for the non-I/O FET. This segmentation allows each FET type to receive the appropriate oxide treatment independently, achieving the required threshold voltage differentiation without requiring a single complex unified process
Solution Approach 2:
The patent changes the oxidation parameters (thermal vs. non-thermal) to achieve different oxide layer thicknesses and properties. By adjusting these physical parameters during oxide formation, the I/O FET achieves higher threshold voltage through a thicker thermal oxide layer while the non-I/O FET uses a thinner non-thermal oxide layer, simplifying the manufacturing approach
3Productivity
If device dimensions are scaled down to increase storage capacity and processing speed, then productivity is improved, but the manufacturing complexity and difficulty increase
Solution Approach 1:
The gate replacement process is designed to be universal by accommodating both I/O FETs and non-I/O FETs with different oxide requirements through a single integrated process flow. The process can selectively apply thermal or non-thermal oxide formation to different FET regions, maintaining productivity benefits of scaling while managing the complexity of diverse threshold voltage requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of FETs with varying threshold voltages without compromising device size or manufacturing cost, while minimizing hot carrier effects and maintaining performance.
Implementation Method 1
forming a thermal oxide layer on the I/O FET gate structure
Implementation Method 2
forming a non-thermal oxide layer on the non-I/O FET gate structure
Data Source
AI summary
A semiconductor device with different gate structures and a method of fabricating the same are disclosed. The a method includes forming a fin structure on a substrate, forming a thermal oxide layer on top and side surfaces of the fin structure, forming a polysilicon structure on the thermal oxide layer, doping portions of the fin structure uncovered by the polysilicon structure to form doped fin portions, forming a nitride layer on the polysilicon structure and the thermal oxide layer, forming an oxide layer on the nitride layer, doping the nitride layer with halogen ions, forming a source/drain region in the fin structure and adjacent to the polysilicon structure, and replacing the polysilicon structure with a gate structure.