Multi-Gain LNA Paths for Low Current and High Linearity

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Solution Overview

Problem

Conventional low noise amplifiers (LNAs) face challenges in maintaining high linearity and noise figure while adjusting gain over a wide dynamic range, often resulting in impedance mismatch and distortion when reducing current to control gain, and attenuators fail to achieve desired power management and linearity.

Innovation Solution

A low noise amplifier architecture using multiple transistor paths with selectively shut-off FETs, configured as common source and cascode, and switches to maintain consistent impedance and linearity, allowing for adjustable gain modes including zero or negative gain in active bypass mode, while reducing current consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the gain of the LNA is reduced by controlling the bias of the common gate FET, then the current consumption is reduced, but the linearity of the LNA deteriorates

Engineering Contradiction:
Improvecurrent consumptionVSAvoidlinearity
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The LNA is divided into multiple parallel paths (first path with first common source FET and first common gate FET, second path with second common source FET and second common gate FET) that can be independently controlled. This segmentation allows selective activation of paths based on signal strength, enabling current reduction by deactivating paths rather than reducing bias on active FETs, thereby maintaining linearity in active paths.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic gain control by selectively enabling or disabling entire paths based on signal strength detection. Switches control the activation of each path, allowing the system to transition between high-gain mode (both paths active for weak signals) and low-gain mode (single path active for strong signals), optimizing current consumption while maintaining performance.

Inventive Principle:
Principle #15Dynamics

2Use of energy by moving object

If the current is reduced by controlling the bias to adjust gain, then the power consumption is reduced, but the impedance match at the input deteriorates

Engineering Contradiction:
Improvepower consumptionVSAvoidimpedance match
Core Design Contradiction:
Use of energy by moving objectVSEase of operation

Solution Approach 1:

By segmenting the LNA into multiple parallel paths with independent switch control, the patent maintains consistent input impedance across different gain settings. When paths are selectively enabled or disabled, the remaining active paths maintain their designed impedance characteristics, avoiding the impedance mismatch that would result from continuous bias adjustment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the operational state of FETs from continuous bias adjustment to discrete on/off switching. This parameter change from analog bias control to digital path selection maintains stable impedance characteristics while achieving gain adjustment, as each path is designed to present the correct impedance when active.

Inventive Principle:
Principle #35Parameter changes

3Power

If an attenuator is used to control the gain of the LNA, then the gain can be reduced, but the linearity and power management performance deteriorate

Engineering Contradiction:
Improvegain controlVSAvoidlinearity
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

Instead of using a continuous attenuator, the patent segments the amplification function into discrete parallel paths that can be independently switched. This provides gain control through selective path activation rather than continuous attenuation, maintaining signal integrity and linearity while achieving the desired gain reduction effect.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240146272A1Optimized Multi Gain LNA Enabling Low Current and High Linearity Including Highly Linear Active Bypass
Publication Date: 2024.05.02 PSEMI CORP
  • US20240146272A1 patent drawing
  • US20240146272A1 patent drawing
  • US20240146272A1 patent drawing

AI summary

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.