Multi-Gain Ramp ADC Architecture for Faster Low-Power Conversion
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Solution Overview
Problem
Current analog-to-digital converters (ADCs) in image sensors face challenges with increased conversion time and power consumption as bit resolution increases, particularly due to the inefficiencies in ramp ADC topology, which limits frame rate and dynamic range.
Innovation Solution
The proposed solution involves an analog-to-digital converter architecture that uses multiple amplified analog signals with different gains, a comparison stage with multiple comparators, and a control stage to manage handover points during conversion, allowing for efficient control of a counter stage based on comparison outputs, thereby optimizing conversion speed and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the clock speed is increased to reduce quantisation error, then the conversion speed is improved, but the power consumption increases
Solution Approach 1:
The patent divides the conversion process into multiple segments by using multiple comparators that operate at different clock speeds. Each comparator handles a specific portion of the conversion, allowing the system to achieve high precision without requiring all components to operate at maximum speed continuously, thus reducing overall power consumption.
Solution Approach 2:
The patent employs dynamic clock gating where clock signals are selectively enabled or disabled based on the conversion stage and signal characteristics. This dynamic control allows the system to adjust power consumption in real-time while maintaining the required conversion speed and precision for each specific operation.
2Productivity
If multiple comparators are used to improve conversion speed, then the productivity is improved, but the device complexity increases
Solution Approach 1:
The patent segments the comparison function across multiple comparators, each handling specific portions of the analog signal range or specific bit positions. This segmentation enables parallel processing that increases conversion speed while keeping each individual comparator relatively simple in design.
Solution Approach 2:
The patent introduces a new dimension of control by using multiple clock signals with different frequencies and phases. This allows the system to manage the complexity of multiple comparators through temporal multiplexing and coordinated clocking schemes, transforming the complexity management from spatial to temporal domain.
3Measurement precision
If the steepness of the ramp is reduced to reduce quantisation error, then the measurement precision is improved, but the input range is reduced
Solution Approach 1:
The patent segments the input range handling by using multiple comparators with different ramp steepness characteristics. Each comparator is optimized for specific ranges, allowing the system to maintain fine quantisation steps for precision while collectively covering a wide overall input range through the combination of multiple comparison stages.
Solution Approach 2:
The patent applies local quality by assigning different ramp characteristics to different comparators based on their specific functions. Some comparators use gentler ramps for high-precision low-range measurements, while others use steeper ramps for broader range coverage, optimizing both precision and adaptability in different operating regions.
Data Source
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AI summary
An analog-to-digital converter (110) comprises an analog signal input (122) for receiving an analog signal and an amplifying stage (160) configured to generate a set of N amplified analog signals, where N is an integer ≥2. The set of N signals have different gains. The ADC has a ramp signal input (121) for receiving a ramp signal and a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the set of amplified analog signals (SigG1, SigG2) and to the ramp signal input (121). The comparison stage (120) is configured to compare the amplified analog signals with the ramp signal to provide comparison outputs during a conversion period. A control stage is configured to control the counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.