Multi-Gate Nanostructure Channel Wrapping for 4-Side Gate Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing GAA FET devices and fabrication methods have limitations in achieving optimal control over the channel region, particularly due to the lack of effective control over the fourth side of the channel region, which affects device performance and reliability.
Innovation Solution
The method involves forming a multi-gate semiconductor device by providing a substrate with a fin structure, disposing a dummy gate structure, forming spacers, and removing the dummy gate to form a gate trench, allowing for the deposition of a gate dielectric layer and a conductive gate structure that surrounds the fin on all sides, including the bottom.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a FinFET structure with gate electrode adjacent to three side surfaces is used, then fabrication complexity is reduced compared to GAA FET, but gate control over the channel region is insufficient due to the fourth side being far from the gate electrode
Solution Approach 1:
The patent transitions from a planar FinFET structure to a three-dimensional GAA FET structure where the channel region is surrounded by gate electrodes on all four sides. This dimensional change enables complete gate control over the channel region, eliminating the short-channel effects that plague FinFET designs where the fourth side remains ungated.
Solution Approach 2:
The patent employs a nested fabrication approach where a dummy gate structure is formed first, followed by spacer deposition on its sidewalls, then selective removal to create gate trenches. This nested sequence of operations allows precise formation of the surrounding gate structure while maintaining fabrication control through self-aligned processes.
2Reliability
If existing GAA FET fabrication methods are used, then device performance is improved through fuller depletion, but control over the fourth side of the channel region remains inadequate
Solution Approach 1:
The patent forms a dummy gate structure as a preliminary step before creating the final gate electrodes. This dummy gate serves as a template that guides subsequent spacer formation and gate trench creation, ensuring precise positioning and dimensional control of the surrounding gate structure that will fully deplete the channel region.
Solution Approach 2:
The patent introduces spacers as intermediary structures formed on the sidewalls of the dummy gate. These spacers act as mediators that define the precise location and dimensions of the gate trenches, enabling accurate formation of the surrounding gate electrodes with controlled spacing from the channel region.
Data Source
AI summary
A multi-gate semiconductor device includes a plurality of nanostructures vertically stacked over a substrate, a gate dielectric layer wrapping around the plurality of nanostructures, a gate conductive structure over the gate dielectric layer, and a first insulating spacer alongside the gate conductive structure and over the plurality of nanostructures. The first insulating spacer is in direct contact with the gate conductive structure and the gate dielectric layer.