Multi-Gate E-FET for Compact Compound Semiconductor ESD Protection

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Solution Overview

Problem

Compound semiconductor devices, particularly high electron mobility transistors (HEMT) used in RF circuits, face challenges with large chip size due to the need for numerous series-connected E-FET diodes for effective electrostatic discharge (ESD) protection, which increases the overall device area and chip size.

Innovation Solution

The use of multi-gate E-FETs with at least one gate connected to the source, drain, or inter-gate region through resistors reduces the device area and improves linearity by dividing the RF signal across multiple gate electrodes, replacing the conventional series-connected E-FET diodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If series-connected E-FET diodes are used for ESD protection, then ESD protection capability is improved, but device area increases

Engineering Contradiction:
ImproveESD protection capabilityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple E-FET diodes into a single multi-gate E-FET device. Instead of connecting multiple single-gate E-FET diodes in series, the invention integrates their protection functions into one device with multiple gates, thereby achieving the same ESD protection capability while occupying significantly less chip area.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The multi-gate E-FET device performs multiple functions simultaneously: it provides ESD protection for both positive and negative voltage transients while occupying the area of a single device. The multiple gates enable the device to handle bidirectional ESD events, replacing what would traditionally require multiple separate diodes connected in series.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If multiple series-connected E-FET diodes are used, then ESD protection coverage is improved, but chip size increases

Engineering Contradiction:
ImproveESD protection coverageVSAvoidchip size
Core Design Contradiction:
ReliabilityVSVolume of stationary object

Solution Approach 1:

The invention combines the protection coverage of multiple series-connected diodes into a single multi-gate E-FET device. The multiple gates work together to provide comprehensive ESD protection for both polarities, achieving the same coverage as several diodes would provide while occupying minimal chip volume.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If series-connected E-FET diodes are used, then ESD protection performance is improved, but device complexity increases

Engineering Contradiction:
ImproveESD protection performanceVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple separate E-FET diode structures into a single integrated multi-gate E-FET device. This integration simplifies the overall device architecture by eliminating the need for multiple discrete components and their interconnections, while maintaining or enhancing ESD protection performance through the coordinated action of multiple gates.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8970998B2Compound semiconductor ESD protection devices
Publication Date: 2015.03.03 WIN SEMICON
  • US8970998B2 patent drawing
  • US8970998B2 patent drawing
  • US8970998B2 patent drawing

AI summary

The present invention relates to compound semiconductor ESD protection devices of three types. The device comprises a multi-gate enhancement mode PET (E-PET). For the type I compound semiconductor ESD protection device, the source electrode is connected to the plural gate electrodes through at least one first resistor, and the drain electrode is connected to the plural gate electrodes through at least one second resistor. For the type II compound semiconductor ESD protection device, at least one of the plural gate electrodes are connected to at least one of the inter-gate regions between two adjacent gate electrodes through at least one fourth resistor. For the type compound semiconductor ESD protection device, the plural gate electrodes are connected to the source or drain electrodes through at least one seventh resistor. Any two gate electrodes in the three types of compound semiconductor ESD protection devices can be connected by a resistor.