Multi-Gate FeFET Memory With Layered Thresholds for Multibit Density

The patent transitions from planar 2D memory cell layouts to a 3D vertical stacking architecture. Multiple ferroelectric layers are stacked vertically above a common channel, enabling multiple bits of data to be stored in a single vertical column. This dimensional change dramatically reduces the area per memory bit while maintaining storage capacity, directly resolving the contradiction between device area and storage efficiency.

The memory cell is segmented into multiple independent ferroelectric layers, each capable of storing one bit of data. These layers are stacked vertically and can be independently controlled through selective gating mechanisms. This segmentation allows parallel storage of multiple bits within a compact footprint, reducing both area and power consumption compared to conventional SRAM cells that require separate transistors for each bit.

The patent employs vertical stacking of multiple ferroelectric layers along the z-axis to increase storage capacity without expanding the lateral footprint. Each layer in the stack represents an additional bit of storage, transforming a single-bit cell into a multi-bit vertical column. This approach directly addresses the limitation of single-bit FeRAM cells by multiplying storage capacity through the vertical dimension while maintaining constant device area.

The shared channel structure serves multiple ferroelectric layers simultaneously, acting as a universal control element for all bits stored in the vertical stack. This multi-functional design allows a single channel to control multiple storage layers, increasing data storage capacity without proportionally increasing device complexity or area, thereby resolving the contradiction between storage capacity and device footprint.