Multi-Gate Switch FET Structure for Higher Breakdown With Low RON
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Solution Overview
Problem
Conventional FETs struggle to meet the demands of high power and high frequency RF applications due to limitations in breakdown voltage, on-resistance, and off-state capacitance.
Innovation Solution
A multi-gate switch FET design is introduced, featuring a semiconductor structure with multiple gates and a conducting region between them, allowing for improved voltage handling and reduced on-resistance by enabling DC bias application between the gates without increasing off-capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional FET structure is used, then device complexity is low, but voltage handling capability and power performance are insufficient
Solution Approach 1:
The patent divides the gate structure into multiple segments (first gate and second gate) positioned at different locations above the channel. This segmentation allows each gate to independently control different portions of the channel, enabling superior voltage handling and power performance while maintaining a manageable device structure that can be integrated into existing semiconductor fabrication processes.
2Strength
If breakdown voltage is increased, then high power capability is improved, but on-resistance increases
Solution Approach 1:
The patent applies local quality by positioning the first and second gates at different locations above the channel, allowing each gate to independently control the electrical characteristics in its respective region. This enables the device to achieve high breakdown voltage where needed while maintaining low on-resistance through optimized local electric field distribution and carrier transport paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-gate switch FET achieves enhanced voltage handling capabilities while minimizing on-resistance and off-state capacitance, thus improving RF performance in high power and high frequency applications.
Implementation Method 1
A multi-gate switch FET design is introduced, featuring a semiconductor structure with multiple gates and a conducting region between them, allowing for improved voltage handling and reduced on-resistance by enabling DC bias application between the gates
Data Source
AI summary
A multi-gate switch field effect transistor, FET, according to some embodiments includes a semiconductor structure, a source contact on the semiconductor structure, and a drain contact on the semiconductor structure. The multi-gate switch FET further includes a first gate on the semiconductor structure between the source contact and the drain contact; and a second gate on the semiconductor structure adjacent to the first gate and between the source contact and the drain contact. The multi-gate switch FET further includes a conducting region in the semiconductor structure between the first gate and the second gate.