Multi-Gate Inverter Circuit With Tunable Trigger Voltage
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Solution Overview
Problem
Conventional inverters have a fixed trigger voltage that is not tunable, limiting the flexibility and efficiency of logic switching operations.
Innovation Solution
Incorporating multi-gated P-channel and N-channel field effect transistors with at least one transistor being VT-programmable, allowing independent biasing of primary and secondary gates to finely tune the trigger voltage through memory windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional inverters use fixed threshold voltage transistors, then the device structure is simple, but the trigger voltage is not tunable and logic switching flexibility is limited
Solution Approach 1:
The transistor gate is divided into multiple independently controllable gates (first gate, second gate, third gate). Each gate can be controlled by separate voltage inputs, allowing the trigger voltage to be tuned by adjusting the combination of gate voltages. This segmentation enables flexible control of the inverter's switching characteristics without changing the basic inverter structure.
Solution Approach 2:
The inverter transitions from using fixed threshold voltage transistors to using transistors with dynamically adjustable threshold voltages. By applying different voltages to the multiple gates, the effective threshold voltage can be changed in real-time, making the trigger voltage tunable and adaptive to different operating conditions.
2Measurement precision
If VT-programmable transistors with multiple gates are used, then the trigger voltage can be precisely tuned, but the device complexity increases
Solution Approach 1:
The gate control is segmented into multiple independent voltage inputs that can be combined to achieve precise trigger voltage tuning. By controlling each gate segment with different voltages, the effective threshold voltage can be adjusted with fine granularity, achieving high precision control.
Solution Approach 2:
The multi-gated transistor structure serves multiple functions: it acts as both the switching element and the voltage tuning mechanism. The same transistor that performs the logic switching also provides the trigger voltage tunability through its multiple gates, eliminating the need for separate tuning circuits.
3Productivity
If fixed trigger voltage is used in conventional inverters, then the device operation is simple, but the logic switching efficiency and memory cell functionality are limited
Solution Approach 1:
The inverter operates with dynamic threshold voltage adjustment rather than fixed threshold voltage. The multiple gates can be programmed with different voltages to optimize the switching characteristics for different logic operations, improving logic switching efficiency and enabling enhanced memory cell functionality.
Solution Approach 2:
The trigger voltage parameter can be changed by adjusting the gate voltages. This allows the inverter to be optimized for different operating conditions, improving logic switching efficiency and enabling additional functionality such as memory cell operations without changing the basic device structure.
Data Source
AI summary
A device with inverter functionality and a tunable trigger voltage includes a PFET and an NFET connected in series. The FETs are multi-gated and at least one FET is a threshold voltage (VT) programmable FET. In some embodiments, both FETs are dual-gated (i.e., have two gates) with at least one gate of the two gates being programmable (i.e., configured for VT programmability). In these embodiments, the device includes an input node connected to primary gates of the FETs and additional nodes connected to VT-programmable secondary gates of the FETs, respectively. Alternatively, the device includes an input node connected to secondary gates of the FETs and additional nodes connected to VT-programmable primary gates of the FETs, respectively. Alternatively, the device includes an input node connected to primary gates of the FETs and another input node connected to secondary gates of the FETs, where the primary gates and/or secondary gates are programmable.