Multi-Gate Isolation Structures for Uniform Gate Cut Profiles
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Solution Overview
Problem
The formation of uneven gate cut features during the fabrication of multi-gate devices, such as gate-all-around transistors, leads to unpredictable threshold voltage and switching characteristics due to the slow etching of gate dielectric layers, which can result in variations in gate structures.
Innovation Solution
The formation of region isolation features and gate cut features is optimized to ensure uniform profiles by selecting widths that prevent etching of the gate dielectric layer along the sidewalls of the region isolation feature, and the gate cut features are designed to avoid cutting into the region isolation feature, maintaining consistent gate structure integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to form gate cut features, then the fabrication process can proceed, but the gate dielectric layer etches slowly causing uneven profiles and unpredictable threshold voltage
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure with specific width dimensions before the etching process. The mandrel is designed with a width that prevents the etch from reaching the gate dielectric layer, ensuring uniform gate cut features are created in advance before final device formation. This preliminary structuring solves the etching uniformity problem by pre-defining the etch stop boundary.
Solution Approach 2:
The patent introduces an intermediary mandrel structure that acts as a mediator between the etching process and the gate dielectric layer. This mandrel serves as a protective intermediary that prevents direct etching of the gate dielectric, thereby achieving uniform gate cut profiles without sacrificing etching speed, as the etch can proceed rapidly through the mandrel material.
2Productivity
If the etching process is accelerated to improve productivity, then fabrication speed increases, but gate dielectric layer integrity is compromised leading to variations in gate structures
Solution Approach 1:
The mandrel structure is formed in advance with predetermined dimensions that serve as an etch stop barrier. This preliminary action allows subsequent etching processes to proceed at higher speeds without risking damage to the gate dielectric layer, as the mandrel already defines the safe etch boundary. The preliminary structuring enables faster fabrication while maintaining gate structure consistency.
Solution Approach 2:
The patent applies beforehand cushioning by creating a protective mandrel structure that cushions or protects the gate dielectric layer from aggressive etching conditions. This prior protective measure allows the use of faster etching parameters without compromising gate dielectric integrity, thereby improving productivity while maintaining reliability.
3Reliability
If gate cut features are formed to extend into the isolation feature, then device isolation is improved, but threshold voltage becomes unpredictable due to etching variations
Solution Approach 1:
The mandrel structure is formed preliminarily with a specific width that defines the precise boundary for gate cut feature formation. This preliminary dimensioning ensures that the gate cut features extend into the isolation feature for proper device isolation, while the mandrel width simultaneously prevents etching into the gate dielectric layer, thereby maintaining predictable threshold voltage.
Solution Approach 2:
The patent applies local quality by creating a mandrel with specific local dimensions that provide different functions at different locations. The mandrel width is locally optimized to prevent etching of the gate dielectric while still allowing gate cut features to extend into the isolation feature where needed, thus achieving both good device isolation and predictable threshold voltage through localized structural optimization.
Data Source
AI summary
A semiconductor structure according to the present disclosure includes a substrate, a first base fin and a second base fin arising from the substrate, an isolation structure disposed between the first base fin and the second base fin, first channel members disposed over the first base fin, second channel members disposed over the second base fin, a region isolation feature extending into the substrate, a first gate structure wrapping around each of the first channel members, second gate structure wrapping around each of the second channel members, a first gate cut feature extending through the first gate structure and into the isolation feature, and a second gate cut feature extending though the second gate structure and into the isolation feature. Each of the first gate cut feature and the second gate cut feature are spaced apart from the region isolation feature.