Intersecting Isolation Trenches for Multi-Gate Structure Segmentation
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Solution Overview
Problem
As semiconductor devices are scaled down, challenges such as merging of adjacent source/drain epitaxial features and gate structures arise, which existing semiconductor fabrication approaches have not adequately addressed, impacting the manufacturing of low-cost, high-performance, and low-power integrated circuits.
Innovation Solution
The implementation of a cut-poly (CPO) process to isolate adjacent gate structures and a cut-metal-gate (CMG) process to divide gate structures into segments, using selective etching and dielectric filling to prevent merging of source/drain and gate features, respectively, while maintaining effective electrostatic control and scaling capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional fabrication approaches are used for scaling, then manufacturing cost is reduced and production efficiency is improved, but merging of adjacent source/drain epitaxial features and gate structures occurs
Solution Approach 1:
The patent applies segmentation by dividing the gate structure into multiple segments using isolation structures. The gate electrode is split into first and second gate electrode segments separated by an isolation structure, which prevents merging of adjacent gate structures while maintaining electrical functionality. This segmentation approach allows continued scaling without the merging problems that plague conventional approaches.
Solution Approach 2:
The patent introduces an intermediary isolation structure between adjacent gate structures and source/drain regions. This isolation structure acts as a mediator that prevents direct contact and merging between adjacent features while allowing each feature to function independently. The isolation structure includes a dielectric material that electrically isolates the gate electrode segments from adjacent structures.
2Area of moving object
If feature sizes are reduced to increase density, then device scaling is achieved, but merging of adjacent structures occurs that compromises device performance
Solution Approach 1:
The gate electrode is segmented into multiple isolated segments, which prevents merging between adjacent structures even as overall device dimensions are reduced. This segmentation maintains electrical isolation and device reliability while enabling higher density through closer spacing of individual device units.
Solution Approach 2:
The patent introduces vertical dimensionality by forming the isolation structure that extends through multiple layers, including the gate electrode layer and adjacent layers. This three-dimensional isolation approach provides robust electrical separation in the vertical direction while allowing horizontal scaling, thereby maintaining reliability during density increases.
3Reliability
If multi-gate structures are implemented to improve electrostatic control, then gate-channel coupling is enhanced, but complexity of fabrication processes increases
Solution Approach 1:
The isolation structure serves multiple functions simultaneously: it electrically isolates gate electrode segments, prevents merging of adjacent structures, provides mechanical support, and defines critical dimensions. This multi-functionality reduces the need for additional specialized process steps, thereby limiting the increase in fabrication complexity despite the enhanced electrostatic control provided by multi-gate structures.
Solution Approach 2:
The isolation structure is formed preliminarily during the gate electrode formation process, before subsequent processing steps. By establishing the isolation features early in the fabrication sequence, the patent avoids adding complex post-processing steps and integrates the isolation function into the existing multi-gate fabrication flow, thereby limiting complexity increases.
Data Source
AI summary
A method of fabricating a semiconductor device includes providing a dummy structure that includes channel layers, inner spacers disposed between adjacent ones of the channel layers, and a gate structure extending lengthwise in a first direction. A first trench extending lengthwise perpendicular to the first direction is formed, which divides the gate structure into segments. A first isolation feature is deposited in the first trench. The method also includes etching the gate structure and the channel layers to form a second trench extending lengthwise in the first direction. The second trench exposes the inner spacers. A second isolation feature is deposited in the second trench. The second isolation feature intersects the first isolation feature in a top view of the semiconductor device.