Multi-Gate LDMOS Structure for High-Voltage Gate Length Limits
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Solution Overview
Problem
Existing LDMOS transistor technologies face challenges in achieving long gate lengths required for high voltage applications, particularly in foundries that use self-aligned contact processes which limit gate length to around 200nm.
Innovation Solution
The semiconductor device employs multiple shorter gates (each equal to or shorter than 300nm) to form a long gate configuration, with a connector physically connecting the gates to achieve the necessary gate length for high voltage applications, thereby overcoming the limitations of foundries using self-aligned contact processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligned contact processes are used in foundries, then manufacturing precision is improved, but gate length is limited to around 200nm which prevents high voltage applications
Solution Approach 1:
The gate is divided into multiple segments (first gate, second gate, third gate) with different lengths. The first gate has a longer length than the second and third gates. This segmentation allows the device to achieve an effective long gate length for high voltage operation while each individual gate segment can be manufactured within the 200nm precision limits of self-aligned contact processes.
Solution Approach 2:
The patent introduces a vertical dimension by stacking gates at different heights and positions. The first gate is positioned at a different vertical level than the second and third gates, allowing them to control different portions of the channel. This dimensional approach enables achieving long gate control without requiring a single extremely long horizontal gate that would exceed manufacturing precision capabilities.
2Reliability
If multiple gates with different lengths are used, then high voltage application capability is achieved, but device complexity increases
Solution Approach 1:
Multiple gates with different lengths are merged into a single integrated structure where the first gate, second gate, and third gate work together to control the channel. The gates are combined such that they share common source and drain regions, and their control functions are merged to achieve enhanced high voltage capability while maintaining a unified device architecture.
Solution Approach 2:
The multi-length gate structure serves multiple functions: the first gate provides primary control for high voltage operation, while the second and third gates provide additional control for optimizing performance at different operating conditions. This universal structure can handle both high voltage and standard voltage applications, making the device adaptable to various operating requirements.
Data Source
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AI summary
Novel semiconductors and fabrication techniques are provided. In various embodiments, a semiconductor includes a source, a drain, a first gate, a second gate, and a channel. The second gate is electrically coupled to the first gate. The first gate and the second gate are configured to control current between the source and the drain. The channel is in contact with the first gate and the second gate. The channel is configured such that the current flows through the channel. Other aspects, embodiments, and features are also claimed and described.