Multi-Gate Oxide Semiconductor Transistor Structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Miniaturization of transistors leads to a decrease in electrical characteristics, such as negative threshold voltage shift and increased subthreshold value, due to reduced channel width, and there is a need for further reduction in off-state current to achieve low power consumption and high integration.
Innovation Solution
A semiconductor device structure is implemented with multiple gate electrode layers, where one gate electrode layer overlaps with the oxide semiconductor layer and the others cover its end portions, along with a stacked oxide semiconductor layer structure, to enhance control over the oxide semiconductor layer and reduce off-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If transistor miniaturization is implemented to reduce power consumption and increase integration, then off-state current is reduced and integration density is improved, but electrical characteristics deteriorate due to reduced channel width causing negative threshold voltage shift and increased subthreshold value
Solution Approach 1:
The gate electrode is divided into multiple gate electrode layers stacked in the channel width direction. Each gate electrode layer independently controls a portion of the oxide semiconductor layer, enabling segmented control of the channel region. This segmentation allows the electric field to be distributed more effectively across the miniaturized transistor structure, maintaining electrical characteristics while achieving reduced off-state current through the multi-layer configuration
Solution Approach 2:
The invention transitions from a conventional single-plane gate structure to a three-dimensional stacked gate structure. By stacking gate electrode layers in the channel width direction rather than relying solely on horizontal expansion, the patent achieves enhanced control over the oxide semiconductor layer without proportionally increasing the transistor footprint. This dimensional change enables maintaining electrical characteristics while supporting miniaturization for reduced power consumption
2Productivity
If transistor miniaturization is implemented to improve integration density, then device size is reduced and integration is enhanced, but electrical characteristics deteriorate due to reduced channel width
Solution Approach 1:
The gate electrode is divided into multiple gate electrode layers stacked in the channel width direction. Each gate electrode layer independently controls a portion of the oxide semiconductor layer, enabling segmented control of the channel region. This segmentation allows the electric field to be distributed more effectively across the miniaturized transistor structure, maintaining electrical characteristics while achieving reduced off-state current through the multi-layer configuration
Solution Approach 2:
The invention transitions from a conventional single-plane gate structure to a three-dimensional stacked gate structure. By stacking gate electrode layers in the channel width direction rather than relying solely on horizontal expansion, the patent achieves enhanced control over the oxide semiconductor layer without proportionally increasing the transistor footprint. This dimensional change enables maintaining electrical characteristics while supporting miniaturization for reduced power consumption
3Reliability
If a thick oxide insulating film is formed between the oxide semiconductor layer and gate electrode layer to supply oxygen and improve reliability, then oxygen supply is enhanced and device reliability is improved, but electric field penetration is reduced making it difficult for the gate electrode layer to control the oxide semiconductor layer
Solution Approach 1:
The gate electrode is divided into multiple gate electrode layers stacked in the channel width direction. Each gate electrode layer independently controls a portion of the oxide semiconductor layer, enabling segmented control of the channel region. This segmentation allows the electric field to be distributed more effectively across the miniaturized transistor structure, maintaining electrical characteristics while achieving reduced off-state current through the multi-layer configuration
Solution Approach 2:
The invention transitions from a conventional single-plane gate structure to a three-dimensional stacked gate structure. By stacking gate electrode layers in the channel width direction rather than relying solely on horizontal expansion, the patent achieves enhanced control over the oxide semiconductor layer without proportionally increasing the transistor footprint. This dimensional change enables maintaining electrical characteristics while supporting miniaturization for reduced power consumption
Data Source
AI summary
A semiconductor device having a structure which can prevent a decrease in electrical characteristics, which becomes more significant with miniaturization of a transistor, is provided. In addition, a highly reliable semiconductor device is provided. The semiconductor device includes a first gate electrode layer, a second gate electrode layer, and a third gate electrode layer, which are each provided separately. The first gate electrode layer overlaps with an oxide semiconductor layer. The second gate electrode layer partly covers one end portion of the oxide semiconductor layer in the channel width direction. The third gate electrode layer partly covers the other end portion of the oxide semiconductor layer in the channel width direction.