Multi-Gate Semiconductor Device with Nitrogen-Built Spacers
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Solution Overview
Problem
As semiconductor devices scale down, there is a need to improve device performance and reliability by reducing parasitic capacitance and enhancing current control capabilities, particularly in multi-gate transistors with three-dimensional channels.
Innovation Solution
The semiconductor device incorporates a first active pattern with first inner gates and nitrogen build-up areas within spacers, along with a second active pattern and corresponding structures, to enhance electrical stability and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pitch size of semiconductor devices is reduced to increase density, then device density is improved, but parasitic capacitance increases causing electrical instability
Solution Approach 1:
The device is divided into multiple active patterns (first and second active patterns) with separate gate structures, allowing independent control and optimization of each segment to manage parasitic effects while maintaining high density
Solution Approach 2:
Inner spacers are introduced as intermediary structures between the source/drain patterns and inner gates, providing electrical isolation and reducing parasitic capacitance coupling between adjacent components
2Reliability
If multi-gate transistor structures are implemented to improve current control, then current control capability is improved, but device complexity increases
Solution Approach 1:
The gate structure is segmented into outer gates and inner gates, with the inner gates positioned between active patterns. This segmentation enables independent control of current flow in different regions, improving overall current control capability while maintaining a systematic approach to managing complexity
Solution Approach 2:
The inner gates serve multiple functions: they control current flow between active patterns, act as electrostatic barriers to suppress short channel effects, and provide a framework for the inner spacer structure, thereby improving current control without proportionally increasing complexity
3Reliability
If inner gates are added between active patterns to reduce parasitic capacitance, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The inner spacers are formed preliminarily between the source/drain patterns and inner gates before final assembly, establishing the correct spatial relationships and reducing parasitic capacitance pathways in advance of subsequent manufacturing steps
Solution Approach 2:
The inner gates are nested between the active patterns, with inner spacers nested between the source/drain patterns and inner gates. This nested configuration maximizes space utilization and reduces parasitic capacitance while following a systematic fabrication approach
Data Source
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AI summary
A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns spaced apart from the first lower pattern in a first direction, a first gate structure including first inner gates between the first lower pattern and a lowermost first sheet pattern of the first sheet patterns, and between each pair of adj acent first sheet patterns, the first inner gates extending in a second direction that intersects the first direction, where each of the first inner gates includes a first gate electrode and a first gate insulating film, first source/drain patterns on the first lower pattern and connected to the first sheet patterns, first inner spacers between the first source/drain patterns and the first inner gates, and first nitrogen build-up areas within the first inner spacers.