Multi-Gate STI Transistor Liners for Low-Noise CMOS Image Sensors
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Solution Overview
Problem
As semiconductor devices, particularly transistors in complementary metal-oxide semiconductor (CMOS) image sensors (CIS) are scaled down for higher resolution, random telegraph signal (RTS) noise and dark current leakage increase due to challenges in further miniaturization, including issues with planar gate electrodes and multi-gate transistors within shallow trench isolation (STI) structures.
Innovation Solution
A multi-gate transistor design is implemented within an STI structure, featuring a first doped liner on inner sidewalls and a second doped liner on outer sidewalls with varying thicknesses to optimize the channel region, reducing noise and minimizing current leakage while maintaining effective operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are scaled down for higher resolution, then device density and resolution are improved, but random telegraph signal noise and dark current leakage increase
Solution Approach 1:
The patent applies different doping types and concentrations to different regions of the STI structure. Specifically, the first doped liner has a first doping type and concentration, while the second doped liner has a second doping type and concentration, creating locally optimized regions that address noise and leakage issues at specific locations without compromising overall device scaling
Solution Approach 2:
The STI structure combines multiple doped liner layers with different material properties (different doping types and concentrations) within a single isolation structure. This composite approach allows simultaneous optimization of electrical characteristics to reduce both RTS noise and dark current leakage while maintaining the isolation function
2Ease of manufacture
If a single doped liner is used in STI structure, then manufacturing is simplified, but channel region optimization is insufficient leading to increased noise and leakage
Solution Approach 1:
The patent introduces spatial variation in doping characteristics within the STI structure. The first doped liner and second doped liner are positioned at different locations (inner and outer portions respectively) with different doping types and concentrations, allowing localized optimization of electrical properties to reduce noise and leakage while maintaining manufacturability through standard doping processes
3Object-affected harmful factors
If doped liners are added to STI structure, then noise and leakage are reduced, but device complexity increases
Solution Approach 1:
The patent divides the STI structure into segmented regions with different doping characteristics. The first doped liner and second doped liner are formed as separate layers with distinct doping types and concentrations, allowing independent optimization of each region's electrical properties to reduce noise and leakage while maintaining a manageable structural complexity
Data Source
AI summary
The present disclosure relates to semiconductor device with a multi-gate structure. The semiconductor device includes a substrate and a doped region disposed within the substrate. A gate electrode is disposed over the doped region, and a source region and a drain region are disposed within the doped region. A shallow trench isolation (STI) structure is disposed within the substrate and laterally surrounds the source region and the drain region. A first doped liner is disposed along the STI structure, where the first doped liner separates the STI structure from the source region and the drain region. A second doped liner is disposed along the STI structure, where the second doped liner is separated from the first doped liner by the STI structure above a bottom surface of the STI structure.