Multi-gate TFT with Recrystallized Channel Grain Sizes
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Solution Overview
Problem
Conventional image display systems with single-gate TFTs suffer from high kink current instability due to excessive voltage differences between the drain and source, which affects display quality and efficiency.
Innovation Solution
A multi-gate TFT structure is implemented with a silicon film layer having non-adjacent first and second crystallization zones, where the second crystallization zone has better conductivity and smaller equivalent resistance, reducing the kink current by operating in a saturation region with a smaller potential difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional single-gate TFT structure is used, then the device complexity is low, but the kink current increases due to excessive voltage difference between drain and source
Solution Approach 1:
The single-gate TFT is divided into multiple sub-TFTs (first sub-TFT, second sub-TFT, third sub-TFT) with separate gate electrodes (first gate electrode, second gate electrode, third gate electrode). This segmentation allows independent control of each sub-TFT, enabling the potential difference between drain and source to be distributed across multiple smaller voltage differences, thereby reducing the kink current while maintaining manageable device complexity
Solution Approach 2:
The patent introduces a vertical stacking dimension by arranging multiple sub-TFTs in series between the source and drain, transforming the conventional planar single-gate structure into a multi-layer vertical structure. This dimensional change enables better voltage distribution and reduced kink current without significantly increasing the lateral footprint of the device
2Reliability
If the voltage difference between drain and source is reduced, then the kink current decreases, but the electron mobility and current drive capability are compromised
Solution Approach 1:
Different gate electrodes (first, second, third gate electrodes) are applied to different sub-TFTs with potentially different gate voltages, creating local quality variations. This allows each sub-TFT to be optimized for specific functions: some sub-TFTs can operate in saturation region to reduce kink current, while others can operate in linear region to maintain current drive capability, achieving both reduced kink current and preserved electron mobility
Solution Approach 2:
The multi-gate TFT structure enables dynamic control of each sub-TFT's operating state through independent gate voltage application. By dynamically adjusting the gate voltages of different sub-TFTs, the device can adaptively switch between saturation and linear operation modes, optimizing the balance between kink current reduction and electron mobility maintenance under different operating conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-gate TFT design enhances current stability by cascading sub-TFTs, reducing kink current and improving overall performance by maintaining consistent current flow through both zones.
Implementation Method 1
a laser beam having a wavelength longer than 400 nanometers illuminates on the silicon film layer. Accordingly, the silicon film layer absorbs a portion of the laser beam and is thus heated to melt
Implementation Method 2
the other portion of the laser beam penetrates through the second crystallization zone of the silicon film layer and is reflected from the reflecting layer to the silicon film layer
Implementation Method 3
the second crystallization zone of the silicon film layer absorbs the reflected laser beam and is heated and recrystallized
Data Source
AI summary
An image display system has a multi-gate thin film transistor (TFT) disposed on a transparent substrate. The multi-gate TFT includes a silicon film layer, a first electrode and a reflecting layer. The silicon film layer is formed on the transparent substrate and has a first crystallization zone and a second crystallization zone, which are not adjacent to each other. A grain size of the first crystallization zone is smaller than a grain size of the second crystallization zone. The first electrode corresponding to the first crystallization zone is disposed on the silicon film layer. The reflecting layer corresponding to the second crystallization zone is disposed on the transparent substrate. The silicon film layer is disposed on the transparent substrate and the reflecting layer.