Multi-gate Transistor Inner Spacer Curvature for Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multi-gate transistors, such as MBC transistors, face issues with insufficient spacing between the gate structure and the epitaxial source/drain feature, leading to leaks and increased parasitic capacitance due to inadequate inner spacer features.
Innovation Solution
The implementation of inner spacer features with a convex or C-shape design, where the gate dielectric layer extends partially between the channel member and the inner spacer feature, ensuring sufficient separation and reducing leakage and parasitic capacitance by preventing the gate electrode from intruding between the connection portion and the inner spacer feature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inner spacer features are used in multi-gate transistors, then the manufacturing process is simple, but the spacing between gate structure and epitaxial source/drain feature is insufficient, resulting in leaks and increased parasitic capacitance
Solution Approach 1:
The inner spacer feature is designed with a convex or C-shaped curved profile instead of a conventional straight or angular shape. This curvature allows the spacer to extend further into the channel region while maintaining adequate spacing from the source/drain, effectively reducing leakage and parasitic capacitance without requiring complex multi-layer structures
Solution Approach 2:
The inner spacer feature extends in multiple spatial dimensions, particularly curving toward the channel region and extending under the gate structure. This three-dimensional configuration provides superior electrical isolation and spacing control compared to conventional two-dimensional planar spacers, reducing parasitic effects while maintaining manufacturability
2Area of stationary object
If the gate structure is placed closer to the source/drain feature to reduce device area, then the device footprint is smaller, but leakage and parasitic capacitance increase due to insufficient spacing
Solution Approach 1:
The convex or C-shaped inner spacer creates an optimized spatial arrangement that allows the gate structure to be positioned closer to the source/drain region, reducing device footprint. The curved profile ensures adequate electrical spacing is maintained even at reduced dimensions, preventing parasitic capacitance increase
Solution Approach 2:
The inner spacer feature is nested within the device structure, extending under the gate and curving toward the channel region. This nested configuration provides maximum spacing efficiency within the available device area, enabling compact design without compromising electrical isolation or increasing parasitic effects
Data Source
AI summary
A semiconductor device according to the present disclosure includes a first channel member including a first channel portion and a first connection portion, a second channel member including a second channel portion and a second connection portion, a gate structure disposed around the first channel portion and the second channel portion, and an inner spacer feature disposed between the first connection portion and the second connection portion. The gate structure includes a gate dielectric layer and a gate electrode. The gate dielectric layer extends partially between the inner spacer feature and the first connection portion and between the inner spacer feature and the second connection portion. The gate electrode does not extend between the inner spacer feature and the first connection portion and between the inner spacer feature and the second connection portion.